臺灣博碩士論文加值系統

目前半導體業的製造廠的工廠佈置方式普遍存在下列若干缺失：１.在製品水準過高，２.在製品在各區之間的搬運距離長且次數頻繁，３.使用中央天車的次數過高，４.生產過程不順暢。半導體產品價格高昂，生產週期極長，倘若能藉著工廠佈置的改善提高其生產效能，縮短生產週期，必可因而增加產量、降低成本，在企業的獲益上將是相當可觀的。
群組技術具有縮短工件搬運距離、使生產流程順暢…等優點，本論文引用的群組技術方法為POC法、Harhalakiis二階段演算法與修訂Harhalakis二階段演算法。我們以數學軟體Maple與程式語言Ｃ撰寫成程式碼，以利群組分析。工廠佈置圖則以各區及各機台間之從至次數，配合各項工廠佈置假設條件以繪圖軟體AutoCAD13繪製完成。建構晶圓生產之系統模擬模式所使用的系統模擬軟體為ProModel，共建構32種不同之模擬模式。評估模式的各項績效指標分別為Operation Rate、總流程時間、在製品水準、平均週期時間與晶圓運送總距離。最後，我們針對模擬結果以２3*４之４因子多變量的實驗設計與Duncan Test進行各項績效評估。模擬結果發現導入群組技術後可使晶圓生產Operation Rate提高，在製品水準降低，總流程時間、平均週期時間與晶圓運送總距離縮短。

Current IC fab layout may have the following disadvantages: high work-in-process (WIP) level, long wafer move distance, and high utilization of interbay automated material handling system (AMHS). Improvement in the fab design can reduce WIP level, decrease wafer move distance, and decrease AMHS utilization.
This research proposes three approaches to apply group technology (GT) to design IC fabs: ROC, Harhalakis two-level, and modified Harhalakis two-level methods. Programming language C combined with Maple are used to implement these algorithms. AutoCAD is used to draw fab layouts. Furthermore, ProModel is used to build simulation models to test the effectiveness of GT algorithms. A 23 x 4 experiment design is used to evaluate the performance of GT algorithms in terms of operation rate, makespan, WIP level, average cycle time, and average wafer move distance. Simulation results show that IC fabs using GT lead to better performance than traditional IC fabs of job shop style.