臺灣博碩士論文加值系統

　　本論文提出一套多值輸入二值輸出積之互斥或和項化簡運算的電路設計方法。其主要目的是為了減少函數中積項的數目，並且減少各積項中literals的數目。
　　我們利用輸入變數指定的方法得到較佳的多值輸入變數，並以合併公式減少函數的積項，以三個擴展公式做迭代運算，使積項的literals數目減少並使函數能夠再利用合併公式，進而得到一個簡化的多值積之互斥或和項表示式。同時，我們亦推導多輸出函數的化簡方法。
　　我們以MATLAB寫成程式來實現上述的演算法則，並對一些測試樣本做實驗。經實驗結果顯示，除了部份函數(如Vg2)。人在大部份的情況下，我們的方法可以簡化函數，並可以得到較少的積項及較少數日的literals。

　　In this paper, we propose a logic circuit design method which is a heuristic algorithm for EXOR with multi-valued inputs two-valued outputs functions. The major objective is to reduce the number of the products and the literals in the function.
　　We can use input variable assignment to get better multi-valued input variables. We use Merge rule to reduce the number of the products. We use three Expand rules to reduce the number of the literals and change the function form to suit merge rule. The simplification algorithm provides a nearly optimal multi-valued EXOR expression which has the minimum number of products and literals.
　　The proposed algorithm is implemented in MATLAB language. Except for vg2, the experimental results shows that we can use our method to simplify functions and get less products and literals.