臺灣博碩士論文加值系統

本論文提出一種設計解碼器的架構，此種架構包含解碼與轉換X86複雜
指令集成為類似精簡指令集。使用這種解碼器的架構可增加處理器在X86
指令上的平行度，與具有較多的微操作碼輸出。此解碼器組成的內容包括
預提起、預解碼、預解碼指令緩衝器與包含監視性執行指令的轉換器。
在預提起器對快取作指令提起的操作上，我們採用一些與其他架構不同的
策略。當指令中包含有條件分支且具有順向短距離目的時，這將會比一般
形式的預提起器作較少的工作，此策略也將配合轉換器中具有監視性執行
指令的形式。 我們使用行為的模擬與真實的X86指令碼作為輸入。而評
估的結果將顯示此轉換的架構能在單一週期內轉換更多的指令。

This thesis proposes a method to design the decoder
architecture, for decoding and translating X86 instructions to
RISC-like instructions. Thedecoder architecture augments X86
instruction level parallelism to the processor and produces more
micro operation outputs. This decoder contains a prefetcher, a
predecoder, a predecoded instruction buffer and instruction
converters with guarded-execution instructions. We adopt some
different strategy in the prefetcher to fetch instructions from
instruction cache. When the instruction path contains a
conditional branch instruction with forward and short distance
target, the prefetcher will be do less job than an ordinary
prefetcher. This strategy will accommodate converters with
guarded-execution instructions. We use a behavior simulation
with real X86 instruction codes. The evaluation results show
that the proposed translating architecture can translate more
instructions every cycle.