|
In this thesis, new design techniques of cryogenic CMOS current
readout structure are proposed, developed, and applied to the
implementation of photon signal readout integrated circuit for
infrared detector array. The silicon readout circuit is an
important interface circuit of detector array and signal
processing stage in the IR image system. To achieve a high
performance readout and fit the cryogenic working characteristic
of IR detector material, new cryogenic CMOS current readout
structures have been developed and fabricated. The functions and
superior readout performance of the proposed new CMOS readout
structure have been verified by simulations and experimental
measurement under 77oK environment. Applications of the proposed
CMOS readout structure on image processing have also been
explored. At first, based on the conventional direct injection
(DI) and buffered direct injection (BDI) readout circuit, a new
CMOS input biasing circuit for infrared detector called the
shared buffer direct injection (SBDI) is designed and proposed.
This new SBDI readout circuit can improve the performance in the
DI and BDI circuit by applying a shared half circuit technique
on the differential pair buffer. It consumes only half area and
power dissipation in the unit cell circuit as compared to the
BDI with good readout performance of high bias stability, low
noise, good threshold control, and high injection efficiency. A
dynamic discharge source follower (DDSF) output stage is also
proposed and analyzed. It can improvethe speed performance of
the conventional source-follower output buffer and consumes only
dynamic power dissipation. The expected performance and
functions have been verified by experimental measurement under
77oK environment. The low power dissipation and small pixel area
of the proposed new SBDI readout circuit make it more suitable
for infrared (IR) readout applications, especially for 2-D focal
plane arrays (FPA) under strict power and area limitations.
Secondly, based on the application of the proposed SBDI input
biasing technique, a new CMOS switch current integration (SCI)
readout structure is proposed and analyzed. The pixel pitch
becomes smaller and the unit cell area is limited due to the
development of large format IR FPA like 64x64 or 128x128. By
applying the proposed share-buffered direct-injection (SBDI)
biasing technique and shared off focal-plane-array (off-FPA)
integration capacitor structure, high-performance readout
interface circuit for the IR FPA is realized with a pixel size
of 50x50 mm2.An experimental 64x64 SCI readout chip has been
designed and fabricated in 0.8 mm double-poly-double-metal
(DPDM) n-well CMOS technology. The measurement results of the
fabricated readout chip at 77oK with 4V and 8V supply voltages
have successfully verified both the readout function and the
performance improvement. The fabricated chip has a maximum
charge capacity of 1.12x108 electrons, a maximum transimpedance
of 1x109 ohms, and an active power dissipation of 30 mW. The
proposed CMOS SCI structure can be applied to various cryogenic
IR FPAs Moreover, based on the proposed SCI readout structure, a
new CMOS readout technique called buffered gate modulation input
(BGMI) circuit is also proposed in this thesis. By applying the
SCI readout structure, this new BGMI circuit can improve the
performance and problem of the conventional gate modulation
input (GMI) with adaptive gain control and current-mode
background suppression. The on-FPA signal processing capability
of BGMI circuit at front stage can reduce the noise effect of
downstream circuit and improve the readout performance.
Moreover, the current-mode background suppression can increase
the signal dynamic range and avoid integrating saturation on
capacitor. An experimental 128x128 BGMI readout chip has been
designed and fabricated in 0.8 mm double-poly-double-metal
(DPDM) n-well CMOS technology. The measurement results of the
fabricated readout chip under 77oK and 5V supply voltage have
successfully verified both readout function and performance
improvement. The fabricated chip has the maximum charge capacity
of 5x107 electrons, the transimpedance of 2.5x109 ohms at 10nA
background current, and the active power dissipation of 40 mW.
The uniformity of current-mode background suppression is 99%. It
has been shown that a high-performance readout interface circuit
for IR FPA with high injection efficiency, high charge
sensitivity, high dynamic range, large storage capacity, and low
noise is realized within the pixel size of 50x50 um2. These
advantageous traits make the BGMI circuit suitable for the
various applications with a wide range of background current.
Finally, the performance and applications of the proposed SCI
structure and BGMI technique on image process is demonstrated
and analyzed in detail. The smart focal plane array with
4-pixels averaging function is also designed and implemented by
applying the SCI structure. The image readout performance of the
proposed new CMOS readout structure in this thesis is improved
by the on-FPA signal processing capability including adaptive
gain control and background suppression. The contrast
enhancement of weak signal, the readout capability of high
contrast image, the background suppression, and the noise
smoothing of degraded image has been demonstrated and verified
by simulations. It is shown that the second-generation readout
circuit with on-FPA signal processing and smart-FPA concept is
achieved by applying the new CMOS readout structures proposed in
this thesis. It is believed that the proposed CMOS current
readout circuit and the associated design methodology offer new
design scope and future feasibility for new-generation readout
ICs of infrared detector array. Further improvement on circuit
performance and practical applications in various image system
including visible and thermal image readout will be explored and
developed in the future.
|