臺灣博碩士論文加值系統

數位濾波器(digital filters) 為數位信號處理系統之重要構成方塊，
其應用領域涵蓋了各種語音、影像、通訊系統等等。由於其應用廣泛，故
如何在各種不同的應用速度要求下都能提出一個最佳化的濾波器架構為一
重要之研究課題。本論文將藉由對有限響應數位濾波器及濾波器群組設計
空間的探討提出有效率的濾波器架構設計。文中之架構包含了各種可程式
化、不可程式化濾波器模組及濾波器群之架構。 在濾波器的可程式化架
構方面，在法則層次，我們結合了Modified Booth乘法及分散式算術並將
其應用於高速可程式化的應用中。經計算得知，我們所推導出的架構相對
於文獻上的架構，可在相同的速度要求下減少約二分之一的硬體需求。此
外，本架構還具有可彈性管線化(flexibly pipelinable)且管線化不會增
加運算延遲(latency)的特點。在不可程式化的架構方面，我們探討了以
記憶體取代運算單元的可行性，這利用半導體技術中記憶體高積集度的特
性，我們可以對濾波器的演算法經適度的推導及安排，有效率地取代高代
價的乘加法運算。此部份，我們提出一個參數化的架構，使我們可以藉由
調整不同的參數值使我們在不同的速度要求及不同的積體電路技術下，都
可以在所推導出的設計空間中找出在符合速度的規格要求下，成本最低的
有效率的濾波器架構。 在濾波器群的架構設計方面，我們首先探討如何
修改一個已經設計好的架構使其可以分時地執行原本須多套硬體的方法，
我們稱之為硬體共用法。並將此一方法應用於多頻系統中的多級濾波器群
的架構。本方法不同於文獻中以原架構中運算單元及暫存器分開考慮的做
法，取而代之的是在不打散原有架構的情況下提出直接修改的方法，故可
保留原有架構規則或合於心縮式陣列的好處，進而得到適合於超大型積體
電路硬體實現的架構。 在實作方面，我們有兩個成功的晶片實作例子提
出。一為應用論文中的有限響應濾波器的架構設計方法於一無限響應濾波
器的濾波器群的共用架構。這個晶片實作由聯華電子完成並整合了一個八
位元微處理器在單晶片中，成功地實現了一極具市場競爭力的低代價、低
成本之語音辨識系統，並己由聯華電子提出多國專利申請。另一晶片實作
則為一1200bps之頻率調變解碼器中所需之兩數位式匹配濾波器，此晶片
則由凌陽科技實作完成。

FIR filters are important building blocks to many DSP
applications.They are widely applied to applications of various
sample rates such asaudio, video or image signal processing or
signal equalization, etc.Due to the wide range of applications,
the study on efficientimplementations to fit for the different
application requirementsbecomes an interesting topic. In this
dissertation, we study this topicby exploring design spaces of
FIR filter modules (singlefilter) and filter banks (multiple
filters). For exploring the design spaces of a single
filter module, weconsider implementations in bit-level
reformulation and theirarchitecture implementation issues. Two
architectures will be proposed.One is for programmable FIR
filters and the other is for fixedcoefficient ones. The
programmable one is derived basing on theModified Booth encoding
of input signals. It performs filter operationsin digit-serial
and is flexibly pipelinable without incurring extra latency.
Comparison results showedthat the resulting architecture takes
only half the cost withoutsacrificing performance compared with
the architecture proposed in theliterature. The fixed
coefficient one is a memory-based architecture.Fixed coefficient
properties allow us to pre-calculate some requiredoperations in
memory to reduce the required numerical operations.
Efficientschemes to store, partition and arrange the pre-
calculated results are studied.The resulting architecture is a
parameterized one such thatthat it can be tuned to fit for
different application specificationrequirements by adjusting the
values of the parameters. For exploring design spaces of
multiple filters, wepropose hardware sharing methods to allow
DSP systems withmultiple filters to share one set of hardware to
perform requiredcomputations. The hardware-sharing method
modifiesa well-designed architecture to make it ready for
performing multiplefilterings. The method preserves the topology
of original architecture.Hence, if the original architecture
features regular or systolic, the sharedarchitecture will also
be regular or systolic.The hardware-sharing method will be
applied to a typical multirate system:tree-structured QMF banks.
The resulting architecture is a highly sharedone. Two
silicon implementations will also be presented in
thisdissertation. The first one is an IIR filter bank which
performs featureextraction for a low cost speech recognition
system. In thisimplementation, we applied the proposed hardware-
sharing method to aDA-based IIR filter architecture and make it
capable of performingmultiple-levels of multirate filter bank
operations. The other one is apair of matched filters for a FSK
decoder. We applied architectureimplementation issues discussed
in this dissertation and sharedthe hardware to only two six-bit
counters. Both systems have been provedfunctional in silicons by
UMC Tech. Co., LTD and Sunplus Tech. Co., LTD,respectively.

Cover
Contents
1 Introduction
1.1 Bit-level considerations
1.2 Algorithm reformulation
1.3 Hardware sharing
1.4 Dissertation organigation
2 Architecture surveys and classifications
2.1 Word-level formulation and implementations
2.2 Bit-level formulations
2.3 Bit-level bit-sliced filter in the j-index
2.4 Bitsliced array of filter in k-index
2.5 Comparisons
2.6 Summaries
3 High-speed programmable FIR filters
3.1 Algorithm formulation
3.2 Architecture design
3.3 Cost comparisons
3.4 Summaries
4 Specification optimized memory-based architectures
4.1 Algorithm formulation
4.2 Architecture design
4.3 Hardware-speed evaluation
4.4 Summaries
5 Hardware sharing gor DSP architectures
5.1 Register duplication achemes
5.2 Register duplication scheme for pipelined architectures
5.3 performance comparisons
5.4 Summaries
6 Hardware sharing for tree-structured QMF banks
6.1 Tree-structure QMF banks
6.2 The sharing architecture
6.3 Scheduling and hardware sharing
6.4 The overall architecture
6.5 Summaries
7 VLSI implementations and application systems
7.1 Tree-structured IIR filter banks using FIR filters
7.2 Digital matched filters for FSK decoder
7.3 Summaries
8 Concluding remarks