臺灣博碩士論文加值系統

　　在深微米（deep sub-micron）的IC設計中，線路的延遲（wire delay）變得愈來愈大，甚至成為整個電路中主要的延遲來源。進行邏輯合成（Iogic synthesis）時，由於無法得知真正的線路分佈，在使用簡易的延遲模式（delay model）下，估得的線路延遲準確度不高。
　　在這篇論文中，我們將邏輯合成和實體設計（physical design）結合成一個反複的程序，以達成電路的高性能需求。在產生佈局之後，就有了線路的電容和電阻值以及分佈狀況，基於這些佈局後的線路資訊，gate sizing 和 buffer insertion 就能夠抽取（extract）出真正的重要路徑（critical paths），再對這些路徑做效能的最佳化。隨後，工程改變的資訊資料庫（engineering change information database）和更改過的電路會傳給定位和繞線（placement and routing）的工具，以漸進（incremental）的方式來調整佈局。然後，再重新對更改後的佈局抽取線路資訊並傳給佈局後的邏輯合成程序，進行另一回合的效能改善。在反複的過程中，邏輯合成和實體設計緊密地結合運作，將電路的效能做最佳化。我們依此發展了一個軟體系統，並針對0.6微米的標準元件庫所合成的標準電路（benchmark circuits）做實驗。一系列的實驗結果顯示了這個系統可以有效地改善電路的效能。

　　In a deep sub-micron IC design, the wire delay becomes more and more significant and even dominant. During logic synthesis, the wire delay estimation is less accurate because of lack of physical design information. In this thesis, we integrate logic synthesis and physical design into an iterative procedure for performance optimization. With accurate wire delay information extracted from the layout, the gate sizing and buffer insertion procedures are able to capture the real critical paths. The engineering change information and changed netlist are passed to the placement and routing tools for incrementally refining the layout. Iteratively, the logic synthesis and physical design processes work together to improve the circuit speed. A software system called KOAN has been implemented. We have tested KOAN on a set of benchmark circuits targeted towards a 0.6-micron library. A series of experiments has been conducted to investigate the effectiveness of the proposed system.