臺灣博碩士論文加值系統

導管暨內插式類比數位轉換器是以〞兩步驟〞架構為藍圖，並結合使
用了內插的技巧，藉以解決傳統上〞快閃式〞類比數位轉換器內比較器數
目過多之缺點，進而達到較小的晶片面積及較少的功率消耗．同時為了避
免因比較器所造成的時間延遲，採用了所謂的導管式設計，縮短資料的存
取時間．　　本論文設計一操作於 10-bit，取樣頻率 20MS/s，電源為
3.3V 的導管暨內插式類比數位轉換器，利用 0.5um CMOS 製程製作晶片
，同時設計一測試電路測試已製作完成的晶片，評估其表現並加以討論．

Pipelined Interpolating A/D Converter is a kind of ADC based
on the "Two-Step" architecture. By using the technique in terms
of"Interpolating", the number of the comparators within the ADC
is reduced, which is large in conventional Flash ADC. This way
also diminishes the die area and the power dissipation of the
chip. Meanwhile, to shorten the data access time, the "Pipeline"
algorithm is adopted. In this dissertation, a 10-bit 20MS/s
Pipelined Interpolating A/D Converter is designed under a low
voltage of 3.3V. The ADC is fabricated in 0.5um CMOS technology.
Also, a testing circuit is designed to evaluate the performance
of the chip.