臺灣博碩士論文加值系統

由於超大型積體電路技術之不斷提昇，封裝(package)技術已成為電
子系統工作速度的瓶頸；為了突破此一瓶頸，多晶片模組(multichip
module)乃應運而生。多晶片模組是將多個晶片放置於同一封裝內，這使
得信號傳輸延遲(propagation delay)、功率消耗(power consumption)、
和電子系統的實際大小等都大幅減小；但是，這也使得接線(
interconnection)密度大幅提高而導致信號失真。為了確保多晶片模組的
性能(performance)，封裝設計者必須著重於接線設計以降低信號失真。
在本論文中，我們針對多晶片模組接線發展了一套模擬系統。這個系統包
含三部分，分別是參數計算器(parameter calculator)、電路模擬器(
circuit simulator)、和電路最佳化器(circuit optimizer)。參數計算
器用以計算接線的傳輸線參數(transmission-line parameter)；所求得
之參數可輸入電路模擬器以決定電路之時域響應(time-domain response)
。如果時域響應不符合電路設計要求，可用電路最佳化器調整接線的寬度
、長度、和間距等幾何參數(geometric parameter)以達到電路設計要求
。為了驗證這個模擬系統之正確性，我們亦將模擬結果與經驗式、參考文
獻、和它模擬系統所得的結果相比較。

To take full advantage of the increased speed and density of
VLSI circuits, multichip modules ( MCMs ) have been developed to
reduce signal delay, power requirements, and the physical size
of electronic systems. However, as more chips are placed in the
same package, the line density will greatly increase. This can
result in serious signal distortions. In order to ensure the
performance of an MCM-based system, the interconnections between
bare chips must be designed carefully.
In this thesis, we develop a dedicated simulation system to
analyze MCM interconnection networks and help the package
designers to find the optimal design. This simulation system
consists of three parts, namely, parameter calculator, circuit
simulator, and circuit optimizer. The parameter calculator
evaluates the transmission-line parameters of interconnections.
These parameters are fed into the circuit simulator to determine
the time-domain response of an MCM interconnection network. If
the circuit responsdoes not satisfy the performance
specifications, the circuit optimizer can help us to find the
optimalhe simulation results are also compared with the results
from empirical formulas, references and another circuit
simulator, HSPICE. Very good agreement is observed.