臺灣博碩士論文加值系統

在IC製程中,晶片在爐管的製造時間比在其它設備中來的長.所以如何用有
效率的方法去整合工廠中的爐管,並與上層的自動化機構相連是相當重要.
因為爐管的操作繁瑣,因此需要一種有效的工具去分析和實現這個系統,在
此乃使用彩色時序裴氏圖去建模.藉由彩色時序裴氏圖來模擬爐管的動態
行為,包括載入,製程,卸下和晶片數不符…等.使用階層式模組化建模的方
法於彩色時序裴式圖的建模中.階層式架構乃藉由分割爐管的動態行為而
使得模型更簡潔,而模組化建模使得模型更有彈性且易於修改.除了建模和
分析外,也設計爐管系統的監控被模擬器.爐管模擬器的建立使得在設計群
組控制器和其上層機器時不需使用真實的設備,且提供了一個類似環境供
上層系統測試之用.最後,將工作單元的觀念融入爐管系統中.而產品製程
時間也將因傳送距離的減少而節省.

In the IC manufacturing, the wafer processing takes much time in
furnaces than other equipment. How to efficiently integrate
furnaces with other automation machines are important. The
thesis aims to model and monitor a furnace workcell.The CTPN
(Colored Timed Petri Net) is used to model the furnace. Based on
CTPN, the dynamic behaviors of the furnace, such as loading,
processing, unloading and wafer count mismatching, can be
emulated the CTPN model is hierarchical and modular. The
hierarchical architecture is built by dividing the behaviors of
the furnace to make the model more compact and the modular
modeling make the model flexible and easy use.In addition to
modeling and analysis, the monitoring of the furnace system is
designed and accomplished. The furnace emulator provides a quasi
environment for upper level system testing. In addition, it
facilitates the design of the group controller without using
true equipment. Finally, the workcell concept is merged into the
furnace system.