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The low voltage IF (intermediate-frequency) limiting amplifier and received signal strenght indicator (RSSI) are widely used the FM modulation in communication systems. The main functions are amplification and limitation signal and measuring received signal strength. There are several IC's products realizing limiting amplifier and RSSI in bipolar technologies. Here we want to implement the low voltage IF limiting amplifier and received signal strength with CMOS technology. The differential amplifier and full wave rectifier circuit were adopted in this circuit. We have shown the results by the experiment. We provide three circuits of the high speed low voltage limiting amplifier, in order to improve the bandwidth. The first circuit is composed of the basic differential amplifier circuit, output stage, and voltage compensation circuit. In the second circuit, we utilize CSCG differential amplifier to improve the operation frequency. The relationship between, the frequency and the numbers of stages in limiting amplifier were discussed. Although the bandwidth of the high speed limiting amplifier is enough, the limiting amplifier just only amplifies the signal that system needed in actual usage. The actual usage of circuit will he improved, if the limiting amplifier needs the function of filter. We compare the performance of three circuits in the chapter 5 for limiting-filtering amplifier and try to implement them in a IC in the future. We have implemented four chips in this paper, each of them was implemented by TSMC 0.8um process, TSMC 0.6 process, UMC 0.8um process, and UMC 0.5 process. The chip of low voltage IF limiting amplifier and RSSI are in good working, others are partial working. The experiment results of the IF limiting amplifier are as follows: the smallest input signal is 15mv, total gain is 60dB, power dissipation is 3mw. The experiment results of RSSI are as follows: the range of the input signal is 15mv to 500mv, the power dissipation is 2mw and the total power dissipation of the chip is 5 mw.
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