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 本篇論文提出長度為二的冪次方之餘弦轉換(Discrete Cosine Transform)與其反轉換計算用之新式心律式架構(Systolic Architectures)。若對輸入資料做有效率的重排，則N點的餘弦轉換可公 式化為N點的快速傅立葉轉換(Fast Fourier Transform)與一個後置調變( Post-modulation)的實部結果；相反的，若對輸出資料做相同之重排，則 N點的反餘弦轉換可公式化為一個前置調變(Pre-modulation)與N點的快速 傅立葉轉換的實部結果，這兩種公式化可分別化成兩個不同類的矩陣分解 ，而這些矩陣分解可直接經由線性心律式陣列(Linear-Connected Systolic Arrays)來實現。在本論文中所提出的方法中，所須用到的基本 處理器(Processors)和乘法器數目僅正比於log2N，與最近其它方法相比 較，本方法具有較低的硬體成本。除此之外，對於量化誤差也在本論文當 中作分析，從分析結果中，可證明:在保持相同水準的雜訊訊號比(Noise- To-Signal)之條件下，若輸入資料長度增加為四倍，則暫存器(Register) 長度必須增加一個額外的位元。
 New systolic architectures for computing the discrete cosine transform (DCT) of length of power 2 and its inverse, are presented in this thesis. With an efficient reordering for the input, the N-point DCT can be formulated as the real part of the N-point fast Fourier transform (FFT) following by a post modulation. In contract, with the same reordering for the output, the N-point inverse discrete cosine transform (IDCT) can be formulated as the real part of a pre-modulation following by the N-point FFT. Both formulations respectively lend themselves to the two different particular matrix factorizations which suggest direct implementations by linearly-connected systolic arrays. In the proposed implementation for the DCT/IDCT, the number of processors and multipliers required are only proportional to log2N, which has lower hardware overheads than other recent implementations. In addition, the quantization error that exhibits the effect of finite precision arithmetic used for hardware realization is analyzed. With the finite-word- length analysis, it is shown that if the length of data sequence is quadrupled, then to maintain the same noise-to-signal ratio, one additional bit must be added to the register length.
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