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在本篇論文當中，我們提出及探討下列結構﹕1) 具高效率面積乘時間
積的非同步乘法器 () 及其在數位訊號處理上之應用。2) 一同步乘法器
() 及根據乘法器架構演生出位元層FIR數位濾波器[MPC1]。上述的乘法器
均以Baugh-Wooley演算法為依歸，其中第一個採用由機率統計所得到的偏
差，再補償給剩存胞元的輸入，其目的是為了保持最小的量化誤差﹔另一
個架構只用全加法器去組成免累加器之FIR數位濾波器。具高效率面積乘
時間積乘法器，在面積方面節省50%，且在完成一個乘法所需時脈數少40%
﹔其他新型架構亦減少遲滯及增加產能。
In this thesis, we propose and explore follows: 1) an
asynchronous area-time efficient multiplier and its
applications in DSP; 2) a synchronous multiplier and bit-level
FIR filter(4-tap) based on the similar structure. In the above
multipliers based on the Baugh-Wooley algorithm, the first one
adopts probabilistic biases obtained and then fed to the inputs
of the retained adder cells in order to keep the quantization
error to a minimum, and the other uses only full adder,
organized to form free accumulation FIR digital filter. An area-
time efficient multiplier with the area saving 50% and the
period reduction 40% is achieved and the other novel
architectures reduce their latency and increase their
throughput.
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