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研究生:黃柏勳
研究生(外文):Huang, Po-Shin
論文名稱:以不同型式的金氧半邏輯電路所建構之低功率超大型積體電路細胞元件庫
論文名稱(外文):Design of a Low-Power VLSI Cell Library Exploiting Different Types of CMOS Logic Circuits
指導教授:王進賢
指導教授(外文):Jinn-Shyan Wang
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1998
畢業學年度:86
語文別:中文
論文頁數:74
中文關鍵詞:低功率細胞元金氧半超大型積體電路邏輯元件庫
外文關鍵詞:Low-PowerCMOScell libraryVLSIpass transistorlogic
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本論文提出一種新的細胞元件庫之設計方法,其相當符合低功率VLSI之設
計需求,且可應用在以細胞元為基礎之VLSI設計環境中。所開發出來的元
件庫和現有商用的以細胞元為基礎之VLSI設計工具完全可以搭配。本元件
庫之設計有數項特點:1. 細胞元之電路採用互補式邏輯、傳輸閘式邏輯
及 互補式/傳輸閘式混合邏輯等三種。不同的細胞元採 用不同的
邏輯電路,充分發揮三種邏輯之長處。2. NAND/NOR/OAI等細胞元設計採
用互補式邏輯來設 計,而MUX、XOR及XNOR之類細胞元採用傳輸閘式
邏輯來設計。另外利用互補式/傳輸閘式混合邏輯,設 計出過去元件
庫不曾使用或很少使用之新功能細胞元。3. 新型細胞元若是使用互補式/
傳輸閘式混合邏輯者, 相較於純粹互補式或純粹傳輸閘式的電路,其
特性較 佳。這是因為在新型細胞元之設計時,我們進一步 考量電
晶體尺寸之調整,因此電氣特性更好。4. 無論使用任何種類邏輯所設計
出來的細胞元皆有完全 擺幅的輸出,且沒有LEAN細胞元因回授PMOS電
晶體 機制所產生的時間延遲及功率消耗較大問題,也不會 造成下
一級有直流電能消耗問題。5. 元件庫中不同函數(功能)之細胞元總數增
加,經實驗 證明可進一步讓利用此元件庫所合成電路之功率降低。6.
在我們所增加的細胞元中,細胞元電路的複雜度適度 提高;其功能若
由原來的元件庫中之細胞元來實現 ,需要數個小型細胞元才能完成。
對於特定應用, 使用到本論文所開發出來的元件庫來設計時,使用
到細胞元之個數也可減少。如此一來進一步降低了 電路繞線(
Interconnection)之總長度,而得以減少此一 部份之功率消耗。此種
設計考量對於深次微米時代 之VLSI設計也有重要的意義。所開發出來
的新元件庫,利用MCNC標準測試電路來做實驗時,發現無論在電路之繞線
面積、連線長度及功率消耗之表現上均有相當之改善。利用新元件庫和利
用舊元件庫相比,對於測試電路平均功率改善的幅度達14%,而最大幅度
達約34%。我們也將一個算數運算電路,以所開發出來之細胞元件庫完成
設計,並經由CIC投片至TSMC製造中。由佈局後模擬結果看出,利用新元
件庫和利用舊元件庫相比,對於此一電路之功率改善高達43%。
A cell library which can be used to design a low-power VLSI is
proposed. lsoThe usage of this cell library is compatible with
the existent EDA mm CMOSenvironment.m the post-layout
simulation, the power reduction ration of theThe features of the
proposed cell library include:1. Three kinds of logic style, i.
e. Complementary CMOS logic, Pass-Transistor Logic and Pass-
Transistor/Complementary Mixed CMOS Logic, are used in the
design of cells. Which logic style for each cell is selected is
based on the consideration to achieve the best
performance.2. The NAND/NOR/OAI cells adopt the Complementary
CMOS logic and the MUX/XOR/XNOR cells are composed of the
Pass-Transistor Logic. Additionally, Pass-Transistor/
Complementary Mixed CMOS Logic is applied to design new-
function cells those rarely appear in the conventional cell
library.3. The new cells that adopt the Pass-Transistor/
Complementary Mixed CMOS Logic have better performance than
the cells with the same function but adopting Complementary
CMOS Logic or Pass-Transistor logic. The reason is that the
transistor sizing is considered in advance to achieve better
performance.4. No matter which logic style is exploited, the
output of each cell is designed to have a full swing, which
can avoid the problem due to the feedback mechanism in the
LEAN cell. The mechanism of the feedback PMOS will induce
more gate delay and power consumption.5. The total number of
different functions in the new cell library is increased.
Then, the power consumption of a VLSI design using this cell
library is proved to be lower.6. The function complexity of some
new cells is properly raised. If the same function is
implemented through conventional standard cells, it will
require several small cells to accomplish. Thus, a given
application may require less gate count when using the new
cell library. By the way, the total interconnection length
will also be shortened, and the power consumption can be
further reduced. This property is important for deep-sub-
micron VLSI designs.The MCNC Logic Synthesis 91 benchmark
circuits are designed by using the newly developed cell library.
It is found that the chip area, interconnectionlength and power
consumption are significantly reduced. The power reductionratio
is 14% on average and maximum reduction ration can be up to
34%,comparing to designs using the conventional cell library.A
4-bit ALU is alsoimplemented and fabricated using the proposed
cell library in a 0.6mm CMOSprocess. From the post-layout
simulation, the power reduction ration of thedesign utilizing
the new cell library is up to 43% as compared with thatdesigned
with the conventional cell library.
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