臺灣博碩士論文加值系統

隨著積體電路的複雜度愈來愈高，在閘層電路考慮可測試設計已經不
適合。 為了減少產品的上市時間， 並且確保產品是可測試的，可測試設
計已從閘層移往較高的層次(行為層，暫存器傳輸層)。 本篇論文就 是
在較高的層次上考慮可測試設計，經由修改電路行為描述的方式，解決在
內建自我測試的環境下，CASE 條件敘述可能會產生的可測試度問題。
修改過後的CASE條件敘述所描述的電路，在內建自我測試的環境下 ，將
能更有效的被測試。

Due to the increasing complexity of integrated circuits(Ics),
it is getting difficult to consider DFT(Design For Testability)
at gate level. To shorten time to market of products,DFT has
been considered at high level (Behavioral Level, Register
Transfer Level ) rather than gate level in recent years. In
this thesis, we present techniques that can be used to deal with
the testabilityproblems caused by "CASE" conditional statement
under Built-In Self-Test(BIST)(BIST) enviroment. We achive this
goal by modifying the original behavioral code. As a result, the
circuits synthesized from the modifiedcode can be effectively
tested.