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In this thesis, linearity analysis, capactior-mismatch error reduction algoritgms,and digital correction algorithms for pipelined analog-to-digital converters are presented. The error sources which limit the resolution of pipelined ADCs are discussed. Systematic analysis of a commutating feedback- capacitor switching (CFCS) technique, which can relax the capacitor matching requirement and cancel the capacitor mismatch to second-order are presented. To evaluate the performance of the CFCS technique, behavior simulation of pipelined ADC is built. Application limitations for the CFCS technique are discussed, and new CFCS applications which have several advantages over the original architectures are found. The improvement of the CFCS technique on SNDR(signal to noise + distortion ratio) are discussed. Moreover, two new techniques suitable for pipelined ADCs are proposed. The first technique, called stage-switching,has a 3dB improvement of SNDR compared to the CFCS technique. The second technique, called capacitor- permutation, can reduce the capacitor mismatch which exists in CFCS technique. The capacitor-permutation technique does not add circuit complexity or sacrifice conversion speed, and 6dB improvement of SNDR over the CFCS technique can be obtained.
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