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Because of the rapid advance in VLSI technology in recent
years, contem-porary high-performance microprocessors contain
millions of transistors and operate at a clock rate of hundreds
of MHz. In this thesis, we investigate two important design
issues of microprocessor design: clock and power/ground
distribution. The major points in clock distribution design are
to minimize clock transition time, clock phase delay, and clock
skew. The major points in the power/ground distribution design
are to minimize voltage drop and voltage fluctuation on the
chip. In this thesis, an effective pre-layout design flow is
developed to design the clock distribution network and the
power/ground distribution grid for high-performance
microprocessor design. The design flow uses simple algorithms
and a reasonable circuit model to obtain reasonable results
before physical layout design, and thus reduce the tedious
fixing work in layout design. In addition, the design flow is
applied to an example micro-processor that consists of 8
millions of transistors. The results show that the clock skew is
reduced to 1.43% of the clock cycle (5 ns) and the voltage drop
is reduced to 8.63% of the working voltage (2.5 V).
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