臺灣博碩士論文加值系統

目前個人數位助理以及掌上型個人電腦已經慢慢的開始流行. 而其內
部之微處理器, 因產品之特性, 而需體積小, 耗電量少之高效能微處理器
來支援. 目前Apple公司所出的MessagePad 2100機型, 其內部之微處理器
即為Digital與ARM兩家公司所合作之StrongARM SA-110. 在本篇論文
中, 我們依據SA-110的指令集以及指令時間安排(Instruction Timing),
設計了處理器中32位元模式下核心的控制邏輯. 並且將此設計與遞移器,
乘法器, 算術邏輯單元, 系統控制副處理器, 以及資料快取記憶體予以整
合. 在此設計中, 我們以由上而下方式, 定義此微處理器核心中各個
模組的功能, 再由各個模組功能定義所需之控制訊號. 我們利用指令集及
其核心管線特性, 將一個用在每個週期執行多暫存器移轉指令位址計算的
加法器移除. 而利用在執行階段中原本就存在的算術邏輯單元來進行存取
位址的累加. 最後, 我們使用Verilog-XL模擬器來模擬指令執行, 驗
證各個功能單元以及各個指令類別能正確地執行指令.

Currently, the Personal Digital Assistant (PDA) and the
Handheld PC (HPC) get fashionable gradually. Because of the
characteristics of these products,they need high performance
microprocessors of which area size is small and power
dissipation is low. The StrongArm SA-110, developed by Digital
Equipment Corporation in collaboration with ARM Limited, is the
microprocessor inside the MessagePad 2100 model produced by
Apple company. In this thesis, according to the instruction set
and the instruction timing of the SA-110, we design the control
logic for the 32-bit mode processor core,and integrate the
control logic, the barrel shifter, the multiplier, and the ALU
into the processor core. Then, the processor core is combined
with the system control coprocessor and the data cache. At
first, we define the function for each module of this processor
core by top-down method. Then, we define the control signals
that each module needs to complete the defined function. By the
features of the instruction set and the core pipeline, we can
remove the adder that calculates the access address per cycle
when multiple register transfer instructions execute. We replace
the function of this adder with that of the ALU which exists in
the execution stage originally. Finally, we verify the
correctness of the function for each module and that of the
execution for each instruction type with Verilog-XL simulator.