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This dissertation studies several topics on timing simulation,
power estimation and maximization which concern design and test
of digitalcircuits. First, this dissertation proposes a new
approach which canmaximize power dissipation of the digital
circuit during burn-in testing. Next, a compiled-code, parallel
pattern timing simulator which takes account of inertial delays
of logic gates to improve the speed and accuracy for timing
simulation of digital circuits is presented. Finally, the
simulator is applied to power estimation for digital circuits.
First, for increasing power dissipation of burn-in testing, an
approach to generate weighted random patterns which can
maximally excite a circuit during its burn-in testing is
proposed. This approach is based on two sensitivity measures,
transition propagation sensitivity and power weight sensitivity,
and a maximization procedure to obtain signal transition
probability distribution for primary inputs. Then, weighted
random patterns can be generated according to the obtained
probability distribution. It can especially generate weighted
random patterns to excite particularly selected "weak nodes" of
the circuit in order to expose the early failure of these nodes.
Experimental results show that this approach can increase power
dissipation of the total circuit nodes up to 26.68% and
switching activity of particularly selected nodes up to 41.51%
respectively. The proposed approach can be applied to
sequential circuits by modifying the power estimation method and
the calculation of power weight sensitivity. The above
maximization procedure is also modified to estimate the maximum
power dissipation, i.e., the worst case power. The modified
procedure generates a lower bound of the maximum power
dissipation which cannot be obtained by just simulating long
random sequences. For the compiled-code simulator, it
incorporates the parallel pattern strategy and the inertial
delay model. Due to incorporation of the inertial delay model,
the timing simulation is more accurate. Experimental results
show that a high percentage, i.e., 27%, of transitions which are
simulated to occur for the conventional timing simulator should
be eliminated. Also, since the simulator utilizes the parallel
pattern strategy, experimental results show that it surpasses
significantly over the conventional time wheel event-driven
simulator in the simulation speed. For the application to the
power estimation, a probability-based method with inertial delay
model is proposed to estimate the power dissipation for digital
logic circuit. Due to employing the inertial delay model, the
approach is more accurate and the above developed simulator is
used as to verify the estimation error for this approach. For
the estimator, the effect of inertial delay is transformed into
an elimination process of transition probabilities according to
the actual behavior of logic gate.Experimental results on ISCAS
benchmark circuits show that the proposed method is superior to
the previous work. Especially, for majority of large benchmark
circuits, the estimation error is below 10%.
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