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研究生:黃國展
研究生(外文):Huang, Kuo-Chan
論文名稱:數位電路之時序模擬及其在功率估算與最大化之應用
論文名稱(外文):Timing Simulation and Its Applications to Power Estimation and Maximization for Digital Circuits
指導教授:李崇仁李崇仁引用關係
指導教授(外文):Lee Chung-Len
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1998
畢業學年度:86
語文別:中文
論文頁數:91
中文關鍵詞:時序模擬功率估算功率最大化權重隨機圖樣惰性延遲模型熱加速測試
外文關鍵詞:Timing SimulationPower EstimationPower MaximizationWeighted Random PatternInertial Delay ModelBurn-in Testing
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本論文係研究有關數位電路設計測試之時序模擬、功率估算及最大化之諸
問題。首先本論文提出一新方法,可以有效地增加電路在熱加速測試之功
率消耗以達成熱加速測試之目的。再次,本論文也提出一編譯碼平行圖樣
之時序模擬器,藉由考慮邏輯閘之惰性延遲特性,以增進數位邏輯電路時
序模擬之速度與準確度。最後,將此一模擬器推廣應用至數位電路之功率
估算。首先,於增加熱加速測試功率上,本論文提出一方法,以其所產生
之權重隨機圖樣可以在熱加速測試期間儘可能地驅動電路。此一方法利用
兩種靈敏度量測(轉換傳遞靈敏度及功率權重靈敏度)及一最大化程序來獲
得輸入端之信號轉換機率分佈,並且根據所獲得之機率分佈來產生權重隨
機圖樣。特別是此一方法所產生之權重隨機圖樣可以有效地驅動電路內某
些特定選擇之薄弱節點,以期能夠激發這些節點之早期故障。實驗結果顯
示此一方法能增加整個電路的功率消耗最多可達26.68%,對於某些特定選
擇的節點則能增加多達41.51%之切換次數。藉由修改功率估算方法及功率
權重靈敏度計算,此一方法可推廣應用至序向電路。上述之最大化程序可
以被修改應用至最大功率消耗量的估算,其所得之結果優於以模擬一冗長
的隨機圖樣所獲得。再者,本論文提出一結合平行圖樣策略及惰性延遲模
型之編譯碼時序模擬器,得以準確而快速地完成電路之時序模擬。當比較
不同延遲模型的模擬實驗結果時發現,有高比例(約27%)的轉換會因為惰
性延遲的效應而被消去。由於此一模擬器利用平行圖樣策略,其執行速度
遠超過傳統的時間輪事件驅動模擬器。對於功率估算之應用,本論文提出
一機率式之方法來估算數位電路之功率消耗並且利用前述之時序模擬器來
比較其估算誤差。由於使用惰性延遲模型,此一方法可較為準確。根據邏
輯閘的真實行為,此一估算器將惰性延遲的效應轉變成一個轉換機率的消
減程序。由ISCAS電路的實驗結果顯示,此一功率估算方法優於前人的研
究。特別是對於大部份的大型電路,此一功率估算方法所產生之誤差低於
十個百分點。
This dissertation studies several topics on timing simulation,
power estimation and maximization which concern design and test
of digitalcircuits. First, this dissertation proposes a new
approach which canmaximize power dissipation of the digital
circuit during burn-in testing. Next, a compiled-code, parallel
pattern timing simulator which takes account of inertial delays
of logic gates to improve the speed and accuracy for timing
simulation of digital circuits is presented. Finally, the
simulator is applied to power estimation for digital circuits.
First, for increasing power dissipation of burn-in testing, an
approach to generate weighted random patterns which can
maximally excite a circuit during its burn-in testing is
proposed. This approach is based on two sensitivity measures,
transition propagation sensitivity and power weight sensitivity,
and a maximization procedure to obtain signal transition
probability distribution for primary inputs. Then, weighted
random patterns can be generated according to the obtained
probability distribution. It can especially generate weighted
random patterns to excite particularly selected "weak nodes" of
the circuit in order to expose the early failure of these nodes.
Experimental results show that this approach can increase power
dissipation of the total circuit nodes up to 26.68% and
switching activity of particularly selected nodes up to 41.51%
respectively. The proposed approach can be applied to
sequential circuits by modifying the power estimation method and
the calculation of power weight sensitivity. The above
maximization procedure is also modified to estimate the maximum
power dissipation, i.e., the worst case power. The modified
procedure generates a lower bound of the maximum power
dissipation which cannot be obtained by just simulating long
random sequences. For the compiled-code simulator, it
incorporates the parallel pattern strategy and the inertial
delay model. Due to incorporation of the inertial delay model,
the timing simulation is more accurate. Experimental results
show that a high percentage, i.e., 27%, of transitions which are
simulated to occur for the conventional timing simulator should
be eliminated. Also, since the simulator utilizes the parallel
pattern strategy, experimental results show that it surpasses
significantly over the conventional time wheel event-driven
simulator in the simulation speed. For the application to the
power estimation, a probability-based method with inertial delay
model is proposed to estimate the power dissipation for digital
logic circuit. Due to employing the inertial delay model, the
approach is more accurate and the above developed simulator is
used as to verify the estimation error for this approach. For
the estimator, the effect of inertial delay is transformed into
an elimination process of transition probabilities according to
the actual behavior of logic gate.Experimental results on ISCAS
benchmark circuits show that the proposed method is superior to
the previous work. Especially, for majority of large benchmark
circuits, the estimation error is below 10%.
Cover
Abstuact (in Chinese)
Abstuact (in English)
Acknowledgements
Contents
Table Captions
Figure Captions
Chapter 1 Introduction
1.1 Reliability and Burn-in Testing
1.2 Timing Simulation
1.3 Power Dissipation of CMOS Circuits
1.4 Outline of Dissertation
Chapter 2 Maximization of Power Dissipation under Random Excitation for Burn-in Testing
2.1 Preview
2.2 Transition Probability and Switching Activity
2.3 Maximization of Power Dissipation under Random Excitation
2.4 Experimental Results
2.5 Maximization for Sequential Circuits
2.6 Maximum Power Estimation
2.7 Summary
Chapter 3 Compiled-Code Parallel Pattern Timing Simulation with Inertial delay Model
3.1 Preview
3.2 Logic Simulation Based on Inertial Delay Model
3.3 Potential Change Frame and Inertial Function
3.4 Experimental Resulits
3.5 Summary
Chapter 4 Power Dissipation Estimation with Inertial Delay for Digital Circuits
4.1 Preview
4.2 Power Estimation with Inertial Delay
4.3 Experimental Results
4.4 Summary
Chapter 5 Conclusions
Bibliography
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