臺灣博碩士論文加值系統

　　現在的CPU架構都採用pipeline的技術以提高效率，然而pipeline卻引起另一個問題，就是分支指令造成的影響。當分支指令的結果並不是執行fall-through路徑的指令，而是taken路徑的指令時，在pipeline中預先從fall-through路徑所取得的指令必須被flush掉。分支預測可以解決分支指令所造成的問題，這個方法是在compile-time或是run-time時收集分支指令的資料，以便在程式執行時據以做預測，提高pipeline之效能。未來的cpu發展趨勢是將pipeline加長以提高效能。但是當分支預測錯誤時，在pipeline中需被捨棄的指令數目也隨之增加，也就是會損失更多的cycle time。這個結果可能導致增長pipeline的好處反而被抵銷了，因此，分支預測的準確性將扮演更重要的角色。目前這方面已有許多的研究，其中Yale N. Patt的Two-Level-Adaptive Training Branch Prediction為分支預測方法中，準確性最高的一種。但這幾年有論文提出，發現Two-Level-Adaptive Training Branck Prediction中大部份的PHT interference 問題會導致準確度的降低，因此許多的方法被提出以解決這個問題。在此篇論文中我們將提出另一種觀點，就是不以降低interference為目的，而是讓interference發生，再以體制記錄下來，並改以其他的以降低interference為目的，而是讓interference發生，再以硬體機制記錄下來，並改以其他的替代方法預測結果，這個機制稱為XP機制（X Prediction）。以這樣的運作方式，我們可以找出破壞性的　interference，而保留住建設性的interference以獲得更高的準確度。

　　Predict the branch outcomes correctly can avoid pipeline bubbles and thus reduce the attendant loss in performance. The accuracy of branch prediction is especially importan in the future, since the more instruction level parallelism is exploited in high-performance microprocessors the induced penalty will get worse when we make error predition. In this paper, we propose a mechanism, called X-Prediction (eXcellent Prediction), to improve the prediction acculacy and the performance in Two-Level-Adaptive Training Branch Prediction. Because it is not feasible to have a big enough hardware to record the history of branch instruction, several branches must share the same buffer entries, and this causes the so-called interference problem. X-Prediction utilizes a simple hardware to look for the destructive interferences in Two-Level-Adaptive Training Branch Prediction, Then use the auxiliary predictor to make prediction. With simulation assistance, we determine the required parameters in implementing this mechanism. Through delicate simulation with six benchmarks from SPEC92 benchmark suite, we find that its performance is improved over that of Yeh and Patt's in average 2-3%