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研究生:楊振麟
研究生(外文):Yang, Jen-Lin
論文名稱:紅外線電荷耦合原件成像系統中垂直條紋雜訊成因之探討
論文名稱(外文):Studies on Vertical Strip Noise in IRCCD Imaging System
指導教授:龔正博
指導教授(外文):Jeng Gong
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1998
畢業學年度:86
語文別:英文
論文頁數:29
中文關鍵詞:紅外線垂直條紋雜訊
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  在本論文中,我們對部份熱成像系統中靜態垂直條紋雜訊的成因作一探討。我們使用黑體做熱源,以量取紅外線攝影機的熱響應;加上不同的讀取電壓,以獲得影像輸出訊號與讀取電壓之間的關係,而後利用此一關係計算像素與像素間的電 阻電容時間常數(R-C time constants)。在模擬方面,我們一方面使用Medici來模擬元件在讀取電荷時的暫態行為,另一方面使用Hspice來模擬晶片中R-C階梯結構的暫態響應,以觀察各像素讀取電壓不平衡的現象。
  在R-C時間常數的計算結果中,我們發現電荷讀取時間實際上遠比我們所認為的要短暫,經計算後發現確實如此;在Medici暫態模擬中,我們發現只要讀取電壓有0.3mV的差距,就可以造成我們所觀察到的訊號不匹配的狀況;在R-C階梯結構的分析中,我們發現在使用多晶矽作為水平方向間各像素的連結時,各像素讀取電壓會有突波存在,此一突波很可能就是造成此一雜訊的成因。我們發現像素間連結的阻值越小,讀取電壓中的突波也就越小。故像素間連結應採用阻值較小之材料。此外,我們也可藉由調整像素中n+橋的濃度來達到補償訊號不平衡的效果。在不改變原來設計的情形下,把讀取電壓上升時間拉長,對消除雜訊也有效果。


  In this thesis, the vertical strip noise problem of IRCCD camera is analyzed based on the hypothesis that large resistance of polysilicon interconnections which result in large . R-C time delay is the cause of the unevenness in the video outpurts. Thermal response of our IRCCD camera was carefully tested and compared to theoretical values, along with the relation of differences between pixels at different scene temperatures. Video outputs are measured at different transfer gate voltages and at fixed scene temperature. With the relation between output signal magnitudes and transfer gate voltages, R-C time constants formed by polysilicon interconnections and capacitance of CCDs can be calculated and compared to layout extracted values. In this step, we found that the time required for the signal electrons to be read out of PtSi detectors may be far shorter than the clock period we used. The time required for read out is calculated form theoretical model,and is indeed far shorter than the clock period we used.
  From the results of Medici simulation it is found that tranfer gate voltage differences as small as 0.3mV could cause the observed unevenness in the output signals, and the uniformity of video outputs can be regained through proper adjusts of concentrations of n+ bridges. At fixed transfer gate bias, an order of difference in the concentration of n+ bridge will result in signal difference comparable to that we observed.
  Further investigation of R-C ladder structures exist in IRCCD chip with Hspice shown that large R-C time constants will result in overshoots in transfer gate voltages at pixels connected by polysilicon intercnnections, which in turn result in the vertical strip problem. This problem can be relieved by the use of metal interconnections, proper adjust of n+ bridge concentrations,and elimination of spikes in clock patterns.

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