臺灣博碩士論文加值系統

　　在本論文中我們提出一個3.3伏特、14位元解析度、16k取樣速率的類比數位轉換器；此類比數位轉換器包含有：在類比數位轉換方面，具有2.048MHz取樣值的二階開關電容和差調變器，以及在跳取方面，具有128倍超取樣的有限脈衝響應多重階段數位濾波器。二階和差調變器是將具有7k頻寬的語音信號，轉換成2.048MHz資料速率的一位元數位輸出信號，然後再將此一位元信號送入跳取過程濾波器，而跳取過程濾波器是將其轉換成為具有14位元解析度、16k取樣速率的數位輸出資料形式。
　　一般來說，超取樣類比數位轉換器的輸出效能主要是被其類比部份的元件所決定，即是取決於和差調變器的輸出效能。在類比數位轉換方面，和差調變器的架構是非常簡單的，主要包含有：運算放大器、比較器、開關電容積分器。然而，開關電容和差調變器會因為一些非理想的因素，例如有限的放大器增益、時脈導入的雜訊、和電荷在電容間傳輸的精確性等而受影響。為了克服這些上述的問題，本論文選擇了一個具有放大器增益補償、較低的時脈導入雜訊、以及更正確之電荷傳輸的二階和差調變器。
　　一般來說，超取樣類比數位轉換器的晶片面積與功率消耗主要是由跳取過程濾波器所決定，為了要實現一個有效的超取樣類比數位轉換器，在跳取方面，本論文試著設計一個低功率、較有效的晶片面積、與線性相位的數位濾波器；此外，對於低通濾波與速率轉換的過程，本論文將之分成幾個階段，其主要目的是可以有效的降低所需濾波器階數與計算上的複雜度。
　　本論文所採用的二階和差調變器具有80dB以上的信號雜訊比（SNR），但本論文只使用普通增益值的運算放大器即可以達到此要求。跳取過程濾波器則是利用sinc濾波器與Half-band濾波器來實現其硬體電路，這樣的設計方法可以減少硬體與功率消耗。

　　In this thesis, a 3,3-V, 14-bit, 16-ksamples/sec △□ analog to digital converter is proposed. The A/D converter consists of a second-order switched-capacitor (SC) △□ modulator for A/D conversion at a 2.048MHz sampling rate and FIR multi-stage digital filters for decimation with oversampling rate of 128. A speech signal with a bandwidth of 7 kHz is converted to a single-bit digital output signal with a 2.048MHz data rate by the second-order SC △□ modulator, and then the single-bit data stream from the analog △□ modulator is fed into the decimation filter. The decimation filters convert a 2.048MHz single-bit data stream into a 14-bit, 16kHz digital output data format.
　　Generally, the output performance of an oversampling analog to digital converter is determined by the analog components Namely, it is determined by the performance of the △□ modulator. For A/D conversion, the architecture of the △□ modulator is very simple. The △□ modulator consists of several components, such as op-amp, comparators, and switched-capacitors, However, the performance of an SC △□ modulator is typically degraded due to some non-ideal factors, such as finite op-amp gain, clock feedthrough noise, and accuracy of the charge transferring between capacitors. In order to overcome these described problems, a second-order SC △□ modulator with techniques of op-amp gain-compensation, lower clock feedthrough noise, and more exact charge transferring between capacitors is employed for the A/D conversion.
　　The die area and power consumption of oversampling A/D converters are governed largely by the decimation filters. In order to implement an efficient A/D converter, this thesis tries to design a low-power and area-efficient linear phase digital filter for decimation. The low-pass filtering and the rate conversion for decimation are performed in several stages. The partitioning of the stage reduces the needed filter orders and the computational requirements. All digital filters are implemented as linear-phase FIR filters for optimal waveform reproduction and good numeric stability.
　　The SNR of the second-order △□ modulator is more than 80dB; however, this thesis only uses a moderate gain op-amp to design this second-order △□ modulator. The decimation is implemented by sinc filter and half-band filters. This design approach can reduce the hardware cost and power consumption. The simulation shows that the operation works well.