臺灣博碩士論文加值系統

由於網際網路之盛行與版權觀念的建立, 如何確保個人數位資料之隱密性已成為最關注的課題之一.本論文將針對RSA密碼系統之硬體實現作深入的研究,藉由理論推導與實務設計兩方面著手,期能達到即時化密碼系統的目的.首先我們提出二進位齊發式演算法,此演算法主要是運用均等分割乘數的方法, 藉以降低區段內資料的相依關係,加快計算速度並且減少實現硬體的成本,來發展出具有可行性與實用性之演算法.其次,傳統式演算法中高複雜度的餘數修正運算也是另一項電路實現的阻礙,究此問題我們參考現有的無數值比較式商數預估並且配合本論文所提出的雙位元重複式掃描,以簡化商數預估與解決資料收斂的難題.為了進一步提昇密碼系統的效能,我們也提出高階底數齊發式演算法與可調掃描長度度之指數餘數演算法, 來加快加解密演算法的運算速度. 在高階底數齊發式演算法中, 根據問題的徵結我們推導出查表法與管線化商數預估用以控制電路之運算週期,才不致於因演算法底數的增加而加深了電路之邏輯深度, 進而影響系統效能. 另外在產生乘積方面, 則設計了改革式電路以減少現有乘法器的層級, 並且符合快速產生乘積的要求,才不致於使得關鍵性電路的設計而主導整體加解密系統的優劣. 我們藉由以上兩項全新設計來克服高階底數的缺失, 使得高階底數演算法能夠明顯增快加密系統的運算速度.在減少乘法餘數運算方面則提出可調式掃描長度指數餘數演算法, 此法的優點在於可以減少預存指數的硬體成本, 並且提昇預存指數的利用效率, 避免不必要的硬體與時間浪費. 除了上述的三個層級的演算法推導外, 在硬體實現方面我們也完成二進位加解密系統與非同步架構的硬體實現, 因為在本論文中運算電路的設計是採用模組化設計具有簡單化擴展性與規則性的特色, 所以本論文的硬體設計非常適合超大型積體電路的實現.

With the explosion of electronic data communication and computer network,how to ensure the security of transmitted data has become an important topicin current research abd commercial product. Of the existing cryptosystem, we concentrated on the investigation the RSA cryptography. The objective of this thesis is to develop efficient VLSI architectures and their corresponding implementations under limited hardware resources to speed up the encryption and decryption of the RSA cryptosystem. The dominant scheme is therefore how to derive an efficient algorithm and/or architecture for the modular exponentiation which is commonly implementated by performing iteration of modular multiplication. In this thesis, we first propose an efficient algorithm to relax ,the data dependency of intermediate operands and speed up the quotient determination for radix-2 modular multiplication. the relaxation of data dependency is accomplished by applying the partitioning technique during multiplication steps and the quotient determination is simplified using the presented scanning scheme during division steps. The resulting architecture is cost-effective and suitable for VLSI implementation. We also show the extension of the radix-2 modular multiplication to high-radix operation in synchronous architecture and to its asynchronous counterpart. In high-radix modular multiplication, the critical computation path is reduced by applying the quotient pipelining and lookup table techniques. In this way, the critical path can be designed to be independent of the chosen radix. For the asynchronous radix-2 modular multiplication, the micropipeline structure is adopted to achieve a local- synchrnous-global asynchronous architecture, which results in more than 20% speed improvement. Based on the modular multiplication, a run-length scanning scheme is then presented for square-and-multiply exponentiation in RSA cryptosystem. With the so-called run-length scanning modular exponentiation algorithm, it is possible to evaluate the trade-offs between hardware requirement and execution time for different levels of implementations. Finally, we have successfully constructed the basic building blocks and elements for synchronous/asynchrnous structures based on the COMPASS cell library. The resulting architectures have the characteristics of regular structures, modular design and expandable feature,therefore it is very suitable for VLSI implementation.