臺灣博碩士論文加值系統

近年來,在高階且複雜的嵌入式下考慮加速設計的速度成為重要的研究題目.這些改進主要在縮短設計到上市的時間且提供低電量消耗,高效能及改進晶片面積.從特定應用晶片的角度來看,我們可以將最常使用到的副函式轉換成硬體來增加效能.雖然這個方法可能增加晶片面積,但在以速度為前提的考量下,我們仍可得到顯著的成果.
在這篇論文中,我們的目的在提供一些解決方法來減低執行時間及描述我們提出的架構和以IP為基礎的架構之設計流程. 我們著眼於軟/硬體選擇及提升效能的方法.在我們解決問題後,我們將可以滿足使用者的需求.

Recently, to speed up the design cycle at a high level for complex embedded systems has been an active research area. The efforts mainly are focused on improving time-to-market for designing application specific integrated chips subject to given constraints such as low power consumption, high performance, and minimal chip area. In the ASIC point of view, we can transform the most frequently used sub-functions of the program into hardware to increase the performance. Although this scheme may increase the chip area, on the premise of speed-up, we can achieve outstanding result.
In this thesis, our goal is to develop some solution for reducing execution time and describe architecture and design flow of IP-base architecture. We focused on hardware/software selection and the methods of improve the performance. After we solve those questions, we can satisfy the user requirements.

CHAPTER 1 Introduction3
1.1Motivation3
1.2Overview and thesis Organization4
CHAPTER 2 Background7
2.1High performance and low power7
2.2Design time and co-design8
2.3 IP, hardware/software partitioning and pipeline9
CHAPTER 3 IP-Base Architecture11
3.1Intellectual properties description11
3.2Architecture with interconnected IP’s12
3.3Performance improvement by parallelization and pipelining14
3.3.1Parallelize difficulties16
3.3.2Pipeline difficulties18
3.4Advantage19
CHAPTER 4 Design Issues20
4.1Define IP library format23
4.2Functional partition and annotated program code23
4.3Create control data flow graph24
4.3.1Data structure24
4.3.2Cycle and branch25
4.4Parser and compute degree28
4.4.1Problem and solution28
4.4.2ARM profile28
CHAPTER 5 Selection policy and advance29
5.1Delay, area and run times30
5.1.1Cost and profit30
5.2Simple solution31
5.2.1Description31
5.2.2Proof this problem33
5.2.3Solution34
5.3Parallelize solution using critical path35
5.3.1Description35
5.3.2Proof this problem38
5.3.3Solution39
5.3.4Parallelize solution without critical path40
5.4parallelize in hardware and software41
5.5Pipeline stage scheduling42
5.5.1Description42
5.5.2Software collision45
5.5.3Solution50
CHAPTER 6 Experiment53
6.1Experiment tools53
6.2Simulation result54
CHAPTER 7 Conclusion58
7.1Summary58
7.2Future work59
Reference:60

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