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研究生:賴國立
研究生(外文):Gwo Lih Lay
論文名稱:GMSK調變解調器硬體架構之研究
論文名稱(外文):Study on Hardware Architecture of a GMSK Modem
指導教授:方大漸
指導教授(外文):Thomas T. Fang
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:英文
論文頁數:67
中文關鍵詞:高斯最小移鍵符元同步估計和頻率誤差估計器檢波器調變器解調器硬體架構緊密的頻譜
外文關鍵詞:GMSKsymbol timing and frequency offset estimatordetectormodulatordemodulatorhardware architecturecompact spectrum
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高斯最小移鍵(GMSK)是一種擁有固定封包,好的雜訊免疫力和緊密的頻譜的調變技術,其適合應用在衛星通訊和移動性的電波應用。所以一些通訊系統(諸如:歐規的GSM和DECT通訊系統)使用它為其調變方式。本篇論文將介紹已減低複雜度的調變器和解調器的設計。根據S. Mc Grath, C. J. Burkley [1]的模型,我們設計了一個使用單一唯讀記憶體的調變器。並且我們也設計非同調GMSK解調器,其中包括檢波器以及符元同步估計和頻率誤差估計器。這個調變器和解調器的設計在降低複雜度上有令人滿意的表現而且適合VLSI製程。

Gaussian minimum shift keying (GMSK) with constant envelope, good noise immunity and compact spectrum is an attractive modulation technique for satellite communications and mobile radio applications. Some communication systems such as GSM and DECT use GMSK as their modulation method. This paper presents the design of a reduced complexity modulator and demodulator using GMSK. We design a single ROM GMSK modulator according to the model of S. Mc Grath, C. J. Burkley [1]. And we also design noncoherent GMSK demodulator which includes the detector and the symbol timing and frequency offset estimator. Both the modulator and demodulator designs give satisfactory performance at reduced complexity and are suitable for VLSI implementation.

Abstract
Chapter 1 Introduction 1
Chapter 2 System Model2
2.1 Transmitter4
2.2 Receiver5
2.2.1 One-Bit Differential Detector5
2.2.2 Two-Bit Differential Detector9
2.2.3 Differential Phase Detection with Viterbi Decoding12
2.3 Conclusion14
Chapter 3 Symbol Timing and Frequency Offset Estimator15
Chapter 4 Hardware Architecture for the Modulator21
Chapter 5 Hardware Designs for the Demodulator28
5.1 Bandpass Signal to Differential Phase Converter29
5.2 Joint Symbol Timing and Frequency Offset Estimator35
5.3 Decision Device36
5.3.1 One-Bit Differential Detection36
5.3.2 Two-Bit Differential Detection38
5.3.3 Differential Phase Detection with Viterbi Decoding39
Chapter 6 Conclusions50
Appendix IThe Strategy of Selecting Symbol Timing51
Appendix II The Shuffle-Exchange Network 54
Appendix III The Architectures of Demodulator 57
Reference63

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