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研究生:蔡再枝
研究生(外文):Tsai-Chin Tsai
論文名稱:應用能量法分析覆晶型電子構裝之層間應力
指導教授:劉德騏
指導教授(外文):De-Shin Liu
學位類別:碩士
校院名稱:國立中正大學
系所名稱:機械系
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:中文
論文頁數:112
中文關鍵詞:能量法覆晶型電子構裝層間應力
外文關鍵詞:Energy MethodFlip ChipInterlaminar Stress
相關次數:
  • 被引用被引用:4
  • 點閱點閱:182
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
中文摘要:
覆晶( Flip Chip Technology;FC )是利用任何的連接方式將裸晶以表面朝下直接與基板面對面的接合技術。而連結裸晶與基板的導電體可為金屬凸塊( Metal Bumps )、或導電膠,所完成的結構再經過填膠( Underfill )的過程將膠體藉由毛細現象流入裸晶與基板間之細縫內以增加整個覆晶結構的機械強度。覆晶構裝的設計包括其製程設計參數與材料的選擇以及結構尺寸的安排都極為重要,任一因素的設計不良都會影響其品質而導致封裝構件在使用時產生熱疲勞的損壞現像。而由於覆晶構裝本體是由數種不同的材料相疊而成,各層材料熱膨脹係數(Coefficient of Thermal Expansion, CTE)的不同,使得覆晶構裝因熱應力而產生變形、撓曲以至在封裝接合面產生較大的剪應力又是造成損壞的主因。因此建立分析計算的方法以瞭解覆晶構裝中接合面上剪應力的分佈情形就成為極重要的研究課題。
本研究應用能量法以三角級數和做為應力函數推導出多層電子構裝層間應力的解析解,其解均為正弦函數與餘弦函數之級數和,故僅需簡易的程式即可計算覆晶構裝中各種結構參數的改變對其層間應力的影響,以及各種參數的靈敏度,大量縮減了應用其他數值分析法所需要的時間。應用能量法所得的結果與有限元素所得的應力分佈相互比較其結果相符。吾人擴展此法去計算CSP構裝中焊球與其上、下接觸面之層間應力,並與有限元素所得的應力分佈相互比較亦得到良好的結果。最後應用本研究所發展之計算模型來討論各種結構參數的改變對DCA與CSP型覆晶構裝層間應力的影響,從而預估較佳的接合面之材質與厚度。
Abstract
Flip-Chip technology is a method can directly attach silicon die to substrate in which the die is flipped so that the connecting conductor pads on the die surface can set on top of the substrate. The pads on the die surface can be metal bumps or conductive adhesive. Underfill encapsulation is typically performed after the chip has been attached to substrate. A measured amount of encapsulant is dispensed at the perimeter of the chip, and is drawn under the chip by capillary action which can increase the strength of the package and reduce thermal mismatch. The thermal fatigue of Flip-Chip could depend on a number of parameters that related to material, configuration, and manufacturing. One of the main factor led to failure is the coefficient of thermal expansion (CTE) mismatch between two levels of packaging which will cause notably shear stresses in their interconnections. Therefore, it is important to establish the analylitical method to examine the thermal shear stress distribution between packaging layers.
A stress-function-based energy method is developed in this research to evaluate the interfacial shear and peel stresses in a multilayered electronic packaging structure subjected to uniform temperature variation. The stress functions are expressed in terms of sine and cosine trigonometric series. The results for stresses between each layer can also be expressed as a summation of sine and cosine trigonometric series. Simple programming and short CPU time can get accurate stress distribution. Compared with other numerical method, it is easy to implement to study the thermal stress variation by changing of the structural parameters. The thermal stresses predict by this method compared well with finite element results. Next, we extended this method to calculate stress distribution on the top and bottom surface of the solder ball in CSP packaging. The results also compare well with finite element results. We than applied this method to analyze the thermal stress effected by structural modification of DCA and CSP type Flip Chip Packaging so that better geometric shape of the Filip Chip joints can be predicted.
第一章緒論1
1.1簡介電子構裝1
1.2研究動機與目的6
1.3文獻回顧9
第二章應用能量法計算電子構裝層間應力的理論模型13
2.1雙層複合樑層間應力計算公式的推導14
2.2雙層複合樑數值計算實例28
2.3三層複合樑層間應力計算公式的推導31
2.4三層複合樑數值計算實例47
2.5五層複合樑之層間應力計算實例54
第三章Solder Joints的應力分佈65
第四章Flip Chip設計參數分析82
第五章結論與未來研究方向99
附錄A102
附錄B106
參考文獻108
中文參考文獻
1. 張福范 "複合材料層間應力" 1993. 高等教育出版.
英文參考文獻
1. Suhir, E., "Stress Relief in Solder Joints Due to the Application of a Flex Circuit" 1991. ASME J. of Electronic Packaging.
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3. Suhir, E., "How Compliant Should a Die-Attachment be to Protect the Chip From Substrate Bowing?" 1995. Technical Briefs. ASME J. of Electronic Packaging.
4. Eischen, J. W., Everett, J. S., "Thermal Stress Analysis of a Bimaterial Strip Subject to an Axial Temperature Gradient" 1989. ASME J. of Electronic Packaging.
5. Eischen, J. W., Chung, C., Kim, J. H., "Realistic Modeling of Edge Effect Stresses in Bimaterial Elements" 1990. ASME J. of Electronic Packaging.
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8. Pao, Y. H., Eisele, E. "Interfacial Shear and Peel Stresses in Multilayered Thin Stacks Subjected to Uniform Thermal Loading" 1991. ASME J. of Electronic Packaging.
9. Pao, Y. H., Badgley, S., Govila, R., Baumgartner, L., Allor, R., Cooper, R., "Measurement of Mechanical Behavior of High Lead Lead-Tin Solder Joints Subjected to Thermal Cycling" 1992. ASME J. of Electronic Packaging.
10. Yin, W. L., "Thermal Stresses and Free-Edge Effects in Laminated Beams: A Variational Approach Using Stress Functions" 1991. ASME J. of Electronic Packaging.
11. Yin, W. L., "Refined Variational Solutions of the Interfacial Thermal Stresses in a Laminated Beam" 1992. ASME J. of Electronic Packaging.
12. Yin, W. L., "The Effects of Inclined Free Edges on the Thermal Stresses in a Layered Beam" 1993. ASME J. of Electronic Packaging.
13. Yin, W. L., Dale, J. L., "The Effects of Adhesive Nonlinearity on Thermal Stress in Layered Components" 1994. ASME J. of Electronic Packaging.
14. Yin, W. L., "Interfacial Thermal Stresses in Layered Structures : The Stepped Edge Problem" 1995. ASME J. of Electronic Packaging.
15. Mirman, B., "Microelectronics and the Built-Up-Bar Theory" 1992. ASME J. of Electronic Packaging.
16. Mirman, B., "Interlaminar Stresses in Layered Beams" 1992. ASME J. of Electronic Packaging.
17. Cifuentes, A. O., "ElastoPastic Analysis of Bimaterial Beams Subjected to Thermal Loads" 1991. ASME J. of Electronic Packaging.
18. Cifuentes, A. O., "A Note on the Determination of the Thermal Stresses in Multi-Metal Beams Subjected to Temperature Variations" 1991. Technical Briefs. ASME J. of Electronic Packaging.
19. Kuo, A. Y., Chen, K. L., "Effects of Thickness on Thermal Stresses in a Thin Solder or Adhesive Layer" 1992. ASME J. of Electronic Packaging.
20. Yamada, S. E., "A Bonded Joint Analysis for Surface Mount Components" 1992. ASME J. of Electronic Packaging.
21. Conway, H. D., Borgesen, P., Li, C. Y., "Elastic Analysis of Flip-Chip Solder Joints Undergoing Thermal Excursions" 1994. ASME J. of Electronic Packaging.
22. Vandevelde, B., Christiaens, F., Beyne, E., Roggen, J., Peeters, J., Allaert, K., Vandepitte, D., Bergmans, J., "Thermomechanical Models for Leadless Solder Interconnections in Flip Chip Assemblies" 1998. IEEE Trans. Comp. Packaging. and Manufacturing Technology-Part A.
23. Ju, T. H., Lin, W., Lee, Y. C., Liu, J. J., "Effects of Ceramic Ball-Grid-Array Package*s Manufacturing Variations on Solder Joint Reliability" 1994. ASME J. of Electronic Packaging.
24. Heinrich, S. M., Shakya, S., Wang, Y. H., Lee, P. S., Schroeder, S. A., "Improved Yield and Performance of Ball-Grid-Array Packages : Design and Processing Guidelines for Uniform and Nonuniform Arrays" 1996. IEEE Trans. Comp. Packaging. And Manufacturing Technology-Part B.
25. Glaser, J. C., "Thermal Stresses in Compliantly Joined Materials" 1990. ASME J. of Electronic Packaging.
26. Nigro, N. J., Heinrich, S. M., Elkouh, A. F., Zou, X., Fournelle, R., Lee, P. S., "Finite Element Method for Predicting Equilibrium Shapes of Solder Joints" 1993. ASME J. of Electronic Packaging.
27. Krishna, A., Harper, B. D., Lee, J. K., "Finite Element Viscoelastic Analysis of Temperature and Moisture Effects in Electronic Packaging" 1995. ASME J. Electronic Packaging.
28. Zhang, Z., Yao, D., Shang, J. K., "Fatigue Crack Initiation in Solder Joints" 1996. ASME J. of Electronic Packaging.
29. Yao, D., Zhang, Z., Shang, J. K., "An Experimental Technique for Studying Mixed-Mode Fatigue Crack Growth in Solder Joints" 1996. ASME J. of Electronic Packaging.
30. Gektin, V., Avram, B. C., Ames, J., "Coffin-Manson Fatigue Model of Underfilled Flip-Chips" 1997. IEEE Trans. Comp. Packaging. And Manufacturing Technology-Part A.
31. Hannemann, Robert J., Kraus, Allan D., Pecht, Michael, "Physical Architecture of VLSI System" 1994. John Wiley & Sons, Inc.
32. Lau, John H., "Ball Grid Array Technology" 1995. McGraw-Hill, Inc.
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34. Lee, Y. C., Chen, W. T., "Manufacturing Challenges in Electronic Packaging" 1998. Chapman & Hall, Inc.
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