|
[1-1] Cornel Cobianu, Ovidiu Popa, and Dan Dascalu, “On the Electrical Conduction in the Interpolysilicon Dielectric Layers,” IEEE Electron Device Lett., Vol. 14, pp. 213-215, 1993. [1-2] Takashi Ono, “Studies of Thin Poly Si Oxides for E and E2PROM,” IEDM Tech. Dig., pp. 380-383, 1985. [1-3] Jack C. Lee and C. Hu, “Polarity Asymmetry of Oxides Grown on Polycrystalline Silicon,” IEEE Trans. Electron Device, pp. 1063, 1988. [1-4] Chao Sung Lai, Tan Fu Lei, and Chung Len Lee, “The Characteristics of polysilicon Oxide Grown in Pure N2O,” IEEE Trans. Electron Devices, Vol. 43, pp. 326-331, 1996. [1-5] L. Faraone, R. Vibronek, and J. Mc Ginn, “Characterization of thermally oxidized n+ polycrystalline silicon,” IEEE Trans. Electron Device, vol. ED-32, p. 577, Mar. 1985. [1-6] L. Faraone, “Thermal SiO2 films on n+ polycrystalline silicon: Electrical conduction and breakdown,” IEEE Trans. Electron Device, vol. ED-33, p. 1785, Nov. 1986. [1-7] D. P. Shum, H. H. Tseng, Q. M. Paulson, K. M. Chang, and P. J. Tobin, “A highly robust process integration with scaled ONO interpoly dielectrics for embedded nonvolatile memory application,” IEEE Trans. Electron Device, vol. 42, p. 1376, July 1995. [1-8] S. Mori, Y. Y. Araki, M. Sato, H. Meguro, H. Tsunoda, E. Kamiya, K. Yoshikawa, N. Arki, and E. Sakagami, “Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices,” IEEE Trans. Electron Device, vol. 43, p. 47, Jan. 1996. [1-9] M. Lenzlinger, E. H. Snow, J. Appl. Phys., vol. 140, pp.278, 1982. [1-10] Z. H. Liu, P. T. Lai and Y. C. Cheng, “Characterization of charge trapping and high field endurance for 15-nm thermally nitrided oxides,” IEEE Transaction on Electron Devices, vol. 38, no.2, p.344, 1991. [2-1] Y. Nishioka, E. F. da Silva, Jr., Y. Wang and T. P. Ma, “Dramatic improvement of hot-electron-induced interface degradation in MOS structures containing F for Cl in SiO2,” IEEE Electron Device Lett., vol. 9, p. 38, 1988. [2-2] Y. Nishioka, Y. Ohji, K. Mukai, T. Sugano, Y. Wang and T. P. Ma, “Dielectric characteristics of fluorinated ultra dry SiO2,” Appl. Phys. Lett., vol. 54, no. 12, p. 1127, 1989. [2-3] W. Ting, G. Q. Lo, T. Y. Hsieh, D. L. Kwong, J. Kuehne, and C. Magee, “Fluorinated thin SiO2 grown by rapid thermal processing,” Appl. Phys. Lett., vol. 56, p. 2255, 1990. [2-4] G. Q. Lo, W. Ting, D. L. Kwong, J. Kuenhe, and C. Magee, “MOS characteristics of fluorinated gate dielectrics grown by rapid thermal processing in O2 with diluted NF3,” IEEE Electron Device Lett., vol. 11, p. 511, 1990. [2-5] P. J. Wright, M. Wong and K. saraswat, “The effect of fluorine on gate dielectric properties,” in IEDM Tech.Dig., 1987, p. 574. [2-6] P. J. Wright, and K. saraswat, “The effect of fluorine in silicon dioxide gate dielectrics,” IEEE Electron Devices, vol. 36, no. 5, p. 879, 1989. [2-7] H. J. Whitlow et al., “Fluorine in low-pressure chemical vapor deposited W/Si contact structures: Inclusion and thermal stability,” Appl. Phys. Lett., vol. 50, p. 1497, 1987. [2-8] G. Q. Lo, W. Ting, J. H. Ahn, D. L. Kwong, and J. Kuehne, “Thin fluorinated gate dielectrics grown by rapid thermal processing in O2 with diluted NF3,” IEEE Electron Devices, vol. 39, no. 1, p. 148, 1992. [2-9] P. J. Wright, N. Kasai, S. Inoue, and K. saraswat, “Hot-electron immunity of dielectric with fluorine incorporation,” IEEE Electron Device Lett., vol. 10, p. 347, 1989. [2-10] J. Ahn, G. Q. Lo, W. Ting, D. L. Kwong, J. Kuehne, and C. Magee, “Radiation hardened metal-oxide semiconductor devices with gate dielectrics grown by rapid thermal processing in O2 with diluted NF3,” Appl. Phys. Lett., vol. 58, p. 425, 1991. [2-11] Y. Nishioka, K. Ohyu, Y. Ohji, and T. P. Ma, “Channel length and width dependence of hot-carrier hardness in fluorinated MOSFETs,” IEEE Electron Device Lett., vol. 10, p. 540, 1989. [2-12] Y. Nishioka, K. Ohyu, Y Ohji, and T. P. Ma, “ Improving hot-electron hardness of narrow channel MOSFETs by fluorine implantation,” in IEEE Device Research Conf., (Santa Barbara, CA) 1990. [2-13] E. F. da Silva, Jr., Y. Nishioka and T. P. Ma, “Radiation and hot-electron hardened MOS structures based on SiO2 grown in O2+NF3,” in IEDM Tech. Dig., p.848,1987. [2-14] E. F. da Silva, Jr., Y. Nishioka and T. P. Ma, “Radiation response of MOS capacitors containing fluorinated oxides,” IEEE Trans. Nucl. Sci., vol. NS-34, p.1190, 1987. [2-15] T. P. Ma, “Effects of fluorine on MOS properties,” Mat. Res. Soc. Sym. Proc., vol.262, p.741, 1992. [2-16] D. N. Kouvatsos, F. A. Stevie and R. J. Jaccodine, “Interface state density reduction and effect of oxidation temperature on fluorine incorporation and profiling for fluorinated metal oxide semiconductor capacitors,” J. Electrochem. Soc., vol.140, no. 4, p. 1160, 1993. [2-17] M. K. Hatalis, J. H. Kung, J. Kanicki and A. A. Bright, “Effect of gate dielectric on performance of polysilicon thin film transistors”, Mat. Res Soc. Pro., vol. 182, p-357,1990. [2-18] S. Maegawa, T. Ipposhi, S. Maeda, H. Nishimura, T. Ichiki, M. Ashida, O. Tanina, Y. Inoue, T. Nishimura and N. Tsubouchi, “Performance and reliability improvements in poly-Si TFT’s by fluorine implantation into gate poly-Si,” IEEE. Trans. Electron Devices, vol.42, p. 1106, 1995. [2-19] J. W. Park, D. G. Moon, B. T. Ahn and H. B. Im, “Recrystallization of LPCVD amorphous Si films using F+ implantation,” Thin Solid Films, 245, p.228, 1994. [2-20] H. N. Chern, C. L. Lee, and T. F. Lei, “The effects of fluorine passivation on polysilicon thin-film transistors”, IEEE. Trans. Electron Devices, vol.41, no.5, p. 698, 1994. [2-21] S. Maegawa, T. Ipposhi, S. Maeda, H. Nishimura, T. Ichiki, M. Ashida, O. Tanina, Y. Inoue, T. Nishimura and N. Tsubouchi, “Performance and reliability improvements in poly-Si TFT’s by fluorine implantation,” in IEDM Tech. Dig., p.41, 1993. [2-22] M. K. Hatalis, J. H. Kung, J. Kanicki and A. A. Bright, “Effect of gate dielectric on performance of polysilicon thin film transistors”, Mat. Res. Soc. Pro., vol. 182, p-357, 1990. [2-23] S. Mori, Y. Kaneko, N. Arai, Y. Ohshima, H. Araki, K. Narita, E. Sakageminand K. Yoshikawa, “Reliability study of thin inter-poly dielectrics for non-volatile memory application”, in Proc. 28th IRPS, p-132-144, 1990. [2-24] M. Hendriks and C. Mavero, “Phosphorus doped polysilicon for double poly structures,” J. Electrochem. Soc., vol. 138, p-1466, 1991. [2-25] L. Faraone, R. Vibronek, and J. Mc Ginn, “Characterization of thermally oxidized n+ polycrystalline silicon,” IEEE Trans. Electron Devices, vol. ED-32, no.3, p-577, Mar. 1985. [2-26] A. Shintani and H. Nakashima, “Anomalous stress in thermal oxide of polycrystalline Si,” Appl. Phys. Lett., vol. 36, p. 983, 1980. [2-27] M. C. Jun, Y. S. Kim and M. K. Han, “Polycrystalline silicon oxidation method improving surface roughness at the oxide/polycrystalline silicon interface,” Appl. Phys. Lett. 66(17), p. 2206, 1995. [2-28] R., J. Mattauch and W. H. Howie, JR., “Field strength degradation in Si-SiO2 polycrystalline Si structure,” IEEE J. Solid state circuits, vol. 11, no. 10, p732-735, 1995. [2-29] Y. Nishioka, K. Ohyu, Y. Ohji, N. Natuaki, K. Mukai, and T. P. Ma, “Hot-electron hardened Si-gate MOSFET utilizing F implantation,” IEEE Electron Device Lett., vol. 10, p. 141,1989. [2-30] K. Shinada, S. Mori, and Y. Mikata, “Reduction in Polysilicon Oxide Leakage Current by Annealing prier to Oxidation,” J. Electronchem. Soc., vol. 132, pp. 2185, 1985. [2-31] H. Kitajima, Y. Suzki, and S. Saito, “Leakage current reduction submicron channel poly-Si TFT’s,” in Extented Abstract SSDM, 1991, p174-176. [3-1] Yasushiro Nishioka, “Hot-Electron Hardened Si_Gate MOSFET Utilizing F Implantation,”, IEEE Elec. Dev. Lett., vol. 10, pp. 141-143 (1989). [3-2] Kenneth P. MacWilliams, “Improved Hot-Carrier Resistance with Fluorinated Gate Oides,”, IEEE Elec. Dev. Lett., pp. 3, 1990. [3-3] Shye Lin Wu, “Electrical Characteristics of Textured Polysilicon Oxide Prepared by a Low-Temperature Wafer Loading and N2 Preannealing Process,” EDL, pp. 113, 1993. [3-4] G. W. Yoon, “MOS Characteristics of NH3-Nitrided N2O-Grown Oxide,” EDL, pp. 179, 1993. [3-5] Chin Kuo Yang, “Improved Electrical Characteristics of Thin-Film Transistors Fabricated on Nitrogen-Implanted Polysilicon Films,” IEDM, pp. 505, 1994. [3-6] Chao Sung Lai, “The Electrical Characteristics of Polysilicon Oxide Grown in Pure N2O,” EDL, pp. 385, 1995. [3-7] Chao Sung Lai, Tan Fu Lei, and Chung Len Lee, “The Characteristics of Polysilicon Oxide Grown in Pure N2O,” IEEE Trans. Electron Devices, Vol. 43, pp. 326-331, 1996. [3-8] J. H. Klootwijk, “Improvements of Deposited Interpolysilicon Dielectric Characteristics with RTP N2O-Anneal,” EDL, pp. 358, 1996. [3-9] Tzu Yun Chang, Tan Fu Lei, Tien Sheng Chao, Cheng Tung Huang, Shi Kuan Chen, Andy Tuan, Steve Chou, “Improvement of Ultra-Thin 3.3nm Thick Oxide for Co-Salicide Process Using NF3 Annealed Poly-Gate,” JJAP, vol. 38, pp. 2243, 1999. [3-10] Prasenjit Chowdhury et al, Appl. Phys. Lett., Vol. 70, pp. 37-39 (1997). [3-11] Peter J. Wright et al., IEEE Trans. Elec. Dev., Vol. 36, pp879-889 (1989). [3-12] Chyuan-Haur Kao, “The TEOS Oxide Deposited on Phosphorus in-situ/POCL3 Doped polysilicon with Rapid Thermal Annealing in N2O,” TED, pp. 1927, 1998. [3-13] P. Olive, T. N. Nguyen, and B. Ricco, “High-field-induced degradation in ultra-thin SiO2 films,” IEEE Trans. Electron Device, vol. ED-35, p. 2259, 1988. [3-14] S. H. Lee, B. J. Cho, J. C. Kim, and S. H. Choi, “Quasi-breakdown of ultra thin gate oxide under high field stress,” IEDM Tech. Dig., p. 605, 1994. [3-15] R. Moazzami and C. Hu, “Stress-induced current in thin silicon dioxide films,” IEDM Tech. Dig., p. 139, 1992. [3-16] D. J. Dumin and J. R. Maddux, “Correlation of stress-induced leakage current in thin oxids with trap generation inside the oxide,” IEEE Trans. Electron Devices, vol. ED-40, p. 986, 1993. [3-17] J. Maserjian and N. Zamani, “Observation of positively charged state generation near the Si/SiO2 interface during Fowler-Nordheim tunneling,” J. Vac. Sci. Tech., vol. 20, p. 743, 1982. [3-18] N. Matsukawa, S. Yamada, K. Amemiya, and H. Hazama, “A hot hole-indeced low-level leakage current in thin silicon dioxide films,” IEEE Trans. Electron Devices, vol. ED-43, p.1924, 1996. [4-1] Klootwijk, J. H., van Kranenburg, H., Cobianu, C., Petrescu, V., Woerlee, P. H. and Wallinga, H., in Proc. ESSDERC’95, 1995, pp. 383-386. [4-2] Faraone, L., Vibronek, R. D. and McGinn, J. T., IEEE Trans. Electron Dev., 1985, 31, 577. [4-3] Lee, J., Chen, I. C. and Hu, C., IEEE Electron Dev. Lett., 1986, 7, 506-509. [4-4] Chyuan Haur Kao, Chao Sung Lai, and Chung Len Lee, “The TEOS CVD Oxide Deposited on Phosphorus In Situ Doped Polysilicon with Rapid Thermal Annealing,” IEEE Trans. Electron Devices, Vol. 44, pp. 526-528, 1997. [4-5] Chyuan-Haur Kao, “The TEOS Oxide Deposited on Phosphorus in-situ/POCL3 Doped polysilicon with Rapid Thermal Annealing in N2O,” TED, pp. 1927, 1998. [4-6] Lorenzo Faraone, “Thermal SiO2 Films on n+ Polycrystalline Silicon: Electrical Conduction and Breakdown,” TED, pp. 1785, 1986. [4-7] Cornel Cobianu, Ovidiu Popa, and Dan Dascalu, “On the Electrical Conduction in the Interpolysilicon Dielectric Layers,” IEEE Electron Device Lett., Vol. 14, pp. 213-215, 1993. [4-8] J. H. Klootwijk, Weusthof, M. H. H., van Kranenburg, H., Woerlee, P. H. and Wallinga, H., “Improvements of Deposited Interpolysilicon Dielectric Characteristics with RTP N2O-Anneal,” EDL, pp. 358, 1996. [4-9] M. Hendriks and C. Mavero, “Phosphorus Doped Polysilicon for Double Poly Structures: I. morphology and Microstructure and II. Electrical Characteristics,” JEC, pp. 1466, 1991. [4-10] F. S. Becker and S. Rohl, “ Low pressure deposition of doped SiO2 by pyrolysis of tetraethylorthosilicate (TEOS), I. Boron and phosphorus doped films,” J. Electrochem. Soc., vol. 134, no. 6, p. 1555, 1987.
|