臺灣博碩士論文加值系統

由於現場可程式邏輯陣列（Field Programmable Gate Array, FPGA）擁有下列性質:可重複程式性與可重組性，使其應用非常廣泛，如：雛型生產測試，硬體模擬，及特殊應用積體電路的設計等方面。使用FPGA的好處可降低電路設計成本，節省上市時間。而由於FPGA內有許多（數千到上百萬）的可程式元件，在重覆使用後無可避免地會有部分元件損壞，但其餘元件仍是可繼續使用的，在測試之後，我們只要將損壞元件記錄起來，然後在使用電腦輔助設計工具設計及重組電路時只程式化沒故障的元件即可。而由於FPGA的面積和密度日益增大以及內部邏輯單元的增多，我們需要一個有效率且省時省成本的測試方法。
使用內建式自我測試 (BIST) 的方法測試FPGA是一個不錯的選擇，因為FPGA的可重複程式性質，在測試之後，測試電路便可移除，因此不需佔用額外的電路面積，也不會降低使用者自定電路的效能。此外，對於測試機器的需求亦較簡單。在這篇論文中我們以內建式自我測試的方法診斷FPGA中的連線錯誤，我們的方法不需假設FPGA內部的CLBs是好的。其次，可完全測試與正確診斷出所有的單一錯誤，而整個測試（診斷）時間僅與FPGA內部的繞線結構有關，而與晶片的面積大小無關

Field Programmable Gate Array (FPGA) has the following properties: reprogrammability, and reconfigurability. Accordingly, FPGAs is used for many applications, for example, fast prototyping, hardware emulation, and ASIC design. Using FPGA for circuit design can reduce the time-to-market and save many costs. Usually there are many (from thousands to millions) programmable components (logic and interconnect) in FPGAs. It's possible that some components will fail after using many times while others still work normally. Whenever this is true, all we have to do is test the FPGA chip and mark bad components. So when users design a circuit using CAD tools, faulty components can be bypassed during placing and routing (P&R) processes. Because area and density of FPGAs get larger and larger, an efficient test method is needed.
Built-In Self-Test for FPGA is attractive, because the testability is achieved without area overhead and performance penalty (after testing, the BIST logic can be removed and reconfigured for its normal operation). Moreover, the requirement for ATE (automatic test equipment) is much simplified. We present a BIST-based diagnosis method for interconnect faults in FPGA. Our BIST approach has no assumption that the CLBs is fault-free. Besides, all single faults can be detected and diagnosed. The total test (diagnosis) time is short and dependent only on the interconnect structure of FPGA, not on FPGA (die) size.

第一章 簡介1
1. 1 動機與目標1
1. 2 論文大綱4
第二章 背景知識（PRELIMINARY）5
2.1 FPGA 基本架構5
2.2 FPGA實作技術（TECHNOLOGY）6
2.3 FPGA細部結構8
2. 4 錯誤模型（FAULT MODEL）14
2.5 內建式自我測試（BIST）簡介16
第三章 測試架構17
3.1基本架構17
3.2測試程序19
3. 2. 1測試程序TP-119
3.2.2測試程序TP-226
3. 2. 3測試程序TP-338
3. 3診斷程序50
3.3.1測試結果分析50
3.3.2診斷規則61
3. 4效能分析69
3. 5定理與驗證70
第四章 實例說明71
4. 1 XILINX XC4003E簡介71
4. 2 XILINX XC4003E的測試73
4. 3測試時間與比較82
第五章 結論與未來工作84
5. 1 問題討論84
5.2 結論與未來工作84
參考文獻86

[1] "Standard Test Access Port and Boundary-Scan Architecture," IEEE Standard P1149.1-1990, May. 1990.
[2] M. Abramovici, M. A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, W. H. Freeman and Company, 1990.
[3] Neil H.E. Weste, K. Eshraghian, Principles of CMOS VLSI design: a system perspective 2nd ed, ADDISON-WESLEY PUBLISHING COMPANY 1993.
[4] Randy H. Katz, Contemporary Logic Design, The Benjamin/Cummings Publishing Company, Inc 1994.
[5] Jesse H. Jenkins, Designing with FPGAS and CPLDS, PRENTICE HALL Englewood Cliffs, NJ 07632 1994.
[6] John V. Oldfield, Richard C. Dorf, Field Programmable Gate Arrays, Wiley-Interscience 1995.
[7] T. Liu, W. K. Huang, and F. Lombardi, "Testing of uncustomized segmented channel FPGAs," in Proc. ACM Intel. Symp. On FPGAs, pp. 125-131, 1995.
[8] T. Inoue, H. Fujiwara, H. Michinishi, T. Yokohira, and T. Okamoto, "Universal test complexity of field-programmable gate arrays," in Proc. 4th Asian Test Symp., pp. 259-265, 1995.
[9] W. K. Huang and F. Lombardi, "An approach for testing programmable /configurable field programmable gate arrays," in Proc. IEEE 14th VLSI Test Symp., pp. 450-455, 1996.
[10] C. Stroud, S. Konala, P Chen, M Abramovici, "Built-In Self-test of Logic Blocks in FPGAs," in Proc. IEEE 14th VLSI Test Symp., pp. 387-392,1996.
[11] C. Stroud, E. Lee, S. Konala, and M. Abramovici, "Using ILA testing for BIST in FPGAs," in Proc. IEEE Intel. Test Conf., pp. 68-75, 1996.
[12] H. Michinishi, T. Yokohira, and T. Okamoto, T. Inoue, H. Fujiwara, "A test methodology for interconnect structures of LUT-based FPGAs," in Proc. 5th Asian Test Symp., pp. 68-74, 1996.
[13] C. Stroud, E. Lee and M. Abramovici, "BIST-based diagnostic of FPGA logic blocks," in Proc. Intel. Test Symp., 1997.
[14] M. Renovell, J. Figueras and Y. Zorian, "Test of RAM-Based FPGA: Methodology and Application to Interconnect," Proc. IEEE VLSI Test Symp., pp. 230-237, 1997.
[15] M. Renovell, J. Figueras and Y. Zorian, "SRAM-Based FPGA's: Testing the Interconnect/Logic Interface," Proc. 7th Asian Test Symp., pp. 266-271, 1998.
[16] T. Inoue, H. Miyazaki, H. Fujiwara, "Universal Fault Diagnosis for Lookup Table FPGAs," IEEE Design & Test of Computer, special Issue on FPGAs, pp. 39-44, January-March 1998.
[17] C. Stroud, S. Wijesuriya, C. Hamilton, M. Abramovici, "Built-In Self-Test of FPGA Interconnect," Proc. Test Conference, pp. 404-411, 1998.
[18] Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita, "Build-In Self-Test for multiple CLB faults of a LUT Type FPGA," Proc. 7th Asian Test Symp., pp. 272-277, 1998.
[19] Sying-Jyan Wang, Chao-Neng. Huang, "Testing and Diagnosis of Interconnect Structures in FPGAs," Proc. 7th Asian Test Symp., pp. 283-287, 1998.
[20] The Programmable Logic Data book, Xilinx, Inc., 1998.