(3.239.33.139) 您好!臺灣時間:2021/02/27 00:30
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:王志豪
研究生(外文):Chih-Hao Wang
論文名稱:現場可規劃邏輯陣列設計之技術映對研究
論文名稱(外文):Study on Technology Mapping for Lookup-Table Based FPGA Design
指導教授:賴源泰
指導教授(外文):Yen-Tai Lai
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:中文
論文頁數:65
中文關鍵詞:現場可規劃邏輯陣列技術映對可繞性
外文關鍵詞:FPGATechnology MappingRoutability
相關次數:
  • 被引用被引用:1
  • 點閱點閱:76
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
由於現場可規劃邏輯陣列具有可讓使用者自行規劃設計、快速的製程及較低的生產成本的優點,現場可規劃邏輯陣列已經成為最受歡迎的超大型積體電路設計技術。
本論文主要是探討當以現場可規劃邏輯陣列實現組合邏輯電路時如何提高技術應對的可繞度。為了降低接腳與邏輯區塊的比例,我們首先減少接腳的總數。然後,在不增加接腳數目的情況下,進一步去減少所需使用邏輯區塊數。
我們的演算法可分成四個步驟,包括使用角錐結構分割電路,找出所有可實現的邏輯區塊,使用覆蓋節點的技巧將所有的節點指定到適合的區塊之中,及減少使用的邏輯區塊。實驗的結果驗證了我們所使用的演算法是相當有效的。
Because Field Programmable Gate Array (FPGA) has the features of user programmable, short turn-around time and low manufacturing cost, it is most popular technique for VLSI design.
The thesis focuses on increasing routability of technology mapping for Lookup-Table based FPGA to implement a combinational logic circuit. To reduce the of pins-of-cell-- ratio, we first minimize the total number of pins among LUTs. Next, the number of LUTs is further reduced when the number of pins does not increase.
Our algorithm is divided four steps: 1) using cone structure to partition the DAG, 2) using polynomial time algorithm to generate all feasible cones with input number no more than K, 3) using vertex cover based techniques to assign all gates to the feasible cones, and 4) reducing the numbers of LUTs. Experimental results for the benchmark circuits demonstrate the effectiveness of our algorithm.
CHAPTER 1 INTRODUCTION
CHAPTER 2 Preliminaries and Problem Formulation
CHAPTER 3 Technology Mapping
CHAPTER 4 Experimental RESULTS
CHAPTER 5 CONCLUSIONS
APPENDIX
[1] H. Hsieh, et. al “A 9000-Gate User-Programmable Gate
Arrays,” Proc. 1988 CICC, May 1988, pp. 15.3.1-
15.3.7.
[2] H. Hsieh, “Third-generation architecture boosts speed and
density of field-programmable gate array,” Proc. 1990
CICC, pp. 31.2.1-31.2.7, May 1990.
[3] J. Rose, R. J. Francis, P. Chow, and D. Lewis, “The Effect
of Logic Block Complexity on Area of Programmable Gate
Arrays”, Proc. 1989 CICC, pp. 5.3.1-5.3.5, May 1989.
[4] J. Rose, R. J. Francis, D. Lewis, and P. Chow,
“Architecture of Field-Programmable Gate Array: The effect
of Logic Block Functionality of Area Efficiency,” IEEE
Journal of Solid-State Circuits, Vol. 25, No. 5, Oct. 1990,
pp. 1217-1225.
[5] J. Rose and S. Brown, “Flexibility of interconnection
structures for field-programmable gate array,” ISSC, Vol.
26, pp. 277-282, Mar. 1991.
[6] S. Singh, J. Rose, P. Chow, D. Lewis, “The Effect of Logic
Block Architecture on FPGA Performance,” IEEE Journal of
Soild-State Circuits, Vol. 27 No. 3, March 1992, pp.281-287.
[7] P. T. Wang, Y. T, Lai, and K. N. Chen, “A high performance
FPGA with hierarchical interconnection structure,”
ISCAS’94, pp. 4.239-4.242.
[8] The programmable gate array. Xilinx Co., 1992.
[9] R.Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-
Vincentelli, “Improved Logic Synthesis Algorithms for
Table Look Up Architectures,” Proc. IEEE International
Conf. Computer-aided Design, pp. 564-567, Nov.1991.
[10] R. M. Karp and J. P. Roth, “Minimization over Boolean
graphs,” in IBM J. Res. and Development, Apr. 1962.
[11] J. Francis, J. Rose, and K. Chungm “Chortle: A Technology
Mapping Program for Lookup Table-Based Field programmable
Gate Arrays,” Proc, 27th ACM/IEEE Design Automation
Conference, pp. 613-619, June 1990.
[12] J. Francis, J. Rose, and Z. Vranesic, “Chortle-crf: Fast
Technology Mapping for Lookup Table-Based FPGAs,” Proc,
28th ACM/IEEE Design Automation Conference, pp. 248-251,
June 1991.
[13] D. Filo, J. C. Yang, F. Mailhot, and G. De Micheli,
“Technology Mapping for a Two-output RAM-based field
Programmable Gate Array,” Proc. EDAC, pp 534-538, Feb.
1991.
[14] N. Woo, “A Heuristic Method for FPGA Technology Mapping
Based on Edge Visibility,” Proc. 28th ACM/IEEE Design
Automation Conference, pp. 248-251, June 1991.
[15] R. Murgai, N. Shenoy, R. K. Brayton and A.Sangiovanni-
Vincentelli, “Performance Directed Synthesis for Table
Look Up Programmable Gate Arrays,” Proc. IEEE
International Conf. Computer Aided Design, PP. 572-575,
Nov. 1991.
[16] R. Murgai, N. Shenoy, R. K. Brayton and A.Sangiovanni-
Vincentelli, “Performance Directed Synthesis for Table
Look Up Programmable Gate Arrays,” Proc. IEEE
International Conf. Computer Aided Design, PP. 572-575,
Nov. 1991.
[17] R. J. Francis, J. Rose, and Z. Vranesic, “Technology
Mapping for Lookup Table-Based FPGAs for performance,”
Proc. IEEE International Conf. Computer Aided Design, PP.
568-571, Nov. 1991.
[18] J. Cong, Y. Ding, A. Kahug, and P. Trajmar, “An Improved
Graph-Based FPGA Technology Mapping Algorithm for Delay
Optimization”, Proc. ICCD, pp. 154-158, Oct.1992.
[19] J. Cong, Y. Ding, “FlowMap: An optimal technology mapping
algorithm for delay optimization in lookup-table based
FPGA designs”, IEEE Transactions on Computer-Aided Design
of Integrated Circuits and System pp. 1-11 Vol.13 No. 1,
January 1994.
[20] J. Cong. And Y. Ding, “On area/depth trade-off in LUT-
Based FPGA technology mapping,” in Proc. ACM/IEEE Design
Automation Conf.1993, pp. 213-218.
[21] Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C. H.
Wu and Youn-Long Lin, “Combining Technology Mapping and
Placement for Delay-Minimization in FPGA Designs”, IEEE
Transactions on Computer-Aided Design of Integrated
Circuits and System pp. 1076-1084 Vol.14 No. 9, September
1995.
[22] S. Trimberger, and M. R. Chene, “Placement-based
partitioning for lookup-table-based FPGAs”, Proc. ICCD,
pp. 86-90, Oct. 1992.
[23] Martine Schlag, Jackson Kong, and Pak K. Chan,
“Routability-Driven Technology Mapping for Lookup Table-
Based FPGA’s”, IEEE Transactions on Computer-Aided
Design of Integrated Circuits and System pp.13-26 Vol.13
No. 1, January 1994.
[24] N. Togawa, M. Sato and T. Ohtsuki, “Maple: A Simultaneous
Technology Mapping Placement, and Global Routing Algorithm
for Field-Programmable Gate Arrays,” Proc. ICCAD-94, pp.
156-163, 1994.
[25] W. Carter, K. Duong, R. H. Freeman, H. Hsieh, J. Y. Ja, J.
E. Mahoney, L. T. Ngo, and S. L. Sze, “A User
Programmable Reconfigurable Gate Array”, in Proceedings
1986 Custom Integrated Circuits Conference, May 1987, pp.
515-521.
[26] A. El Gamal, “Two-Dimensional Stochastic Model for
Interconnections in Master Slice Integrated Circuits”,
IEEE Transactions on Circuits and System, pp.127-138 Vol.
28 No. 2, February1981.
[27] J. R. Ford and D. R. Fulkerson, Flows in Networks.
Princeton, NJ: Princeton University, 1962.
[28] Aiguo Lu, Erik Dagless, and Jonathan Saul, “DART: Delay
and Routability Driven Technology Mapping for LUT Based
FPGAs”, Proc. ICCD, pp. 409-414, Oct. 1995.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
1. 12. 梁錫華 〈說人‧話文‧道情:記林徽音與凌叔華〉 《聯合文學》 1卷5期 1986年3月。
2. 46. 史書美 〈中國現代文學中的女性自白小說〉 《當代》 1994年3月 95期
3. 48. 林秀玲 〈中國革命和女性解放:茅盾小說中的兩大主題─從女性主義文學批評的觀點間論茅盾及其批判家〉 《中外文學》 18卷10期 1989年10月
4. 52. 王明珂 〈誰的歷史:自傳、傳記與口述歷史的社會記憶本質〉《思與言》34卷3期 1996年9月。
5. 52. 王明珂 〈誰的歷史:自傳、傳記與口述歷史的社會記憶本質〉《思與言》34卷3期 1996年9月。
6. 51. 朱崇儀 〈女性自傳:透過性別來重讀/重塑文類?〉《中外文學》 26卷4期 1997年9月。
7. 51. 朱崇儀 〈女性自傳:透過性別來重讀/重塑文類?〉《中外文學》 26卷4期 1997年9月。
8. 50. 李有成 〈論自傳〉《當代》 56期 1990年12月。
9. 50. 李有成 〈論自傳〉《當代》 56期 1990年12月。
10. 49. 宋德明 〈吳爾芙作品中的女性意識〉 《中外文學》 14卷10期 1986年3月。
11. 11. 吳魯芹 〈維吉尼亞‧吳爾芙(Virginia Woolf)與凌叔華:文章千古事,得失寸心知〉 《傳記文學》 42卷3期 1983年3月。
12. 46. 史書美 〈中國現代文學中的女性自白小說〉 《當代》 1994年3月 95期
13. 48. 林秀玲 〈中國革命和女性解放:茅盾小說中的兩大主題─從女性主義文學批評的觀點間論茅盾及其批判家〉 《中外文學》 18卷10期 1989年10月
14. 47. 呂芳上 〈娜拉出走以後─五四到北伐青年婦女的活動〉 《近代中國》 民81年12月 92期
15. 49. 宋德明 〈吳爾芙作品中的女性意識〉 《中外文學》 14卷10期 1986年3月。
 
系統版面圖檔 系統版面圖檔