臺灣博碩士論文加值系統

國際標準組織內的MPEG發展了一系列MPEG-1和MPEG-2之類的視聽覺壓縮標準，這些音訊編碼標準已被廣泛地應用在通訊、廣播和儲存的領域。為了達成這些應用的即時化，編碼和解碼系統必須使用硬體來完成。本論文設計一即時音訊編碼專用集成電路，此專用集成電路使用心脈式陣列來處理具規則、局部相關資料流的演算法，因此非常適合來完成快速的即時音訊編碼系統。
大多數的MPEG音訊編解碼器使用了像TMS320系列的一般用途數位訊號處理晶片，但單一個晶片不足以完成即時的編碼任務。為了提供一個低成本和即時的編解碼器，這些數位訊號處理晶片必須以特殊指定應用來完成。本論文提出的硬體設計乃以心脈式陣列為基本架構，極適合用來實現MPEG-1和MPEG-2壓縮標準的Layer I、Layer II和Layer III格式之音訊編碼濾波組，因此一濾波組為MPEG音訊編碼中計算量最多者。這個架構只使用了十六個乘法器和加法器來處理所有的分頻濾波組之演算，利用一組RAM來重組資料，以及一些ROM來儲存運算所需的係數，整個架構具有模組化和規則化的特色，非常適合於超大型積體電路的實現。跟現有的數位訊號處理晶片比較，我們的設計具有高硬體使用率和低複雜連接線，因此極適合MPEG音訊即時編碼之實現。

The MPEG (Moving Picture Experts Group) within the International Organization of Standardization (ISO) has developed a series of audio-visual standards known as MPEG-1 and MPEG-2. These audio coding standard are used in a wide variety of fields such as communication, broadcasting, and storage applications. To apply these applications in real-time, it is necessary to implement the encoding and decoding system in hardware. This thesis design an application-specific integrated circuit (ASIC) dedicated to real-time MPEG audio coding algorithms. Our ASIC implementation is based on systolic array architecture which is regular, localized and most suitable for real-time applications.
Most of the MPEG audio codec have been implemented by using a general- purpose DSP chip set such as the TMS320 series, but it is clear that a single conventional DSP has not been able to perform all the task required in real-time. In order to provide a low-cost and real-time codec, the DSP chip sets must be application specific. The systolic array based architecture proposed in this thesis for the filter bank of MPEG audio coding is capable of encoding MPEG-1and MPEG-2 standard audio bitstream for Layer-I, Layer-II and Layer-III. The architecture only uses sixteen multipliers and adders to compute the subband algorithm of the filter bank, one RAM to arrange data and some extra ROM to storage coefficients of computing. It possesses the feature of regularity and modularity, and is thus well suited to VLSI implementation. Compared to existing DSP chip set, our implementation has high utilization rate and low communication complexity, that makes it useful for applications required by MPEG audio coding.

Abstract I
Contents III
Figure CaptionsV
Table CaptionsVIII
CHAPTER 1 Introduction1
1.1 MPEG Audio Coding1
1.2 Analysis Subband Filter Bank4
1.3 Psycho-Acoustic Model5
1.4 Systolic Array6
1.5 Organization of This Thesis7
CHAPTER 2 Perceptual Coding of Digital Audio Signals8
2.1 Generic Perceptual Coding Concept8
2.2 Human Auditory Perception10
2.3 Auditory Masking Effect12
2.4 Transform Coding (TC) and Subband Coding (SBC)16
CHAPTER 3 An Overview of the MPEG Audio Compression Algorithm19
3.1 Basic Structure of ISO/MPEG/Audio Codec20
3.2 MPEG-1 Audio Coding21
3.2.1 Layer I, Layer II, and Layer III Coding Scheme21
3.2.2 Filter Bank24
3.2.3 Psycho-acoustic Model26
3.2.4 Bit-Stream Structure21
3.3 MPEG-229
CHAPTER 4 The Algorithm and Architecture of Subband Filter Bank31
4.1 Systolic Array31
4.1.1 The Properties of Systolic Array31
4.1.2 The Design Process of Systolic Array32
4.2 The Design Algorithm of Subband Filter Bank34
4.3 Mapping the Filter Bank Algorithm onto Systolic Array38
4.3.1 Windowing Subalgorithm39
4.3.2 DCT Subalgorithm46
4.4 The Combination of Windowing Part and DCT Part53
CHAPTER 5 The Practical Architecture and Simulation Result of Polyphase Filter Bank56
5.1 Circuit Simulation 56
5.2 Proposed Architecture of the Polyphase Filter Bank57
5.2.1 Windowing and DCT Unit58
5.2.2 Data Arrange Unit63
5.2.3 The Sort Unit66
5.2.4 The Control Unit67
5.2.5 Simulation of Subband Filter Bank69
CAHPTER 6 CONCLUSIONS70
References71

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