Cover
CONTENTS
FIGURE CAPTIONS
TABLE CAPTIONS
PUBLICATION LIST
ABSTRACT
CHAPTER 1. INTRODUCTION
1-1 Image Sequence filtering
1-2 Why Systolic Architectures?
1-3 Design Criteria and Optimality Criteria for VLSI Systolic arrays
1 -4 Organization of the Thesis
CHAPTER 2. MAPPING METODLOGY
2-1 Single Assignment Code
2-2 Deriving a Localized DG from the Algorithm
2-3 Mapping the DG to a Systolic Array
CHAPTER 3. ALGORITHMS
3-1 Morphological Operations
3-2 Distance Transformation
3-3 Median-Related Filtering
3-4 Full Search Block Matching Algorithm
CHAPTER 4. SYSTOLIC ARRAY PROCESSORS OF THE MIN/MAX OPERATION
4-1 Algorithms for min/max operator
4-2 Clock Cycle Reduction by Parallel Processing
CHAPTER 5. SYSTOLIC ARRAY PROCESSORS OF MEDIAN FILTERING
5-1 Data Dependence
5-2 Mapping DG to Systolic Array Processors
5-3 The Bit-Level Algorithm
5-4 The Modified Algorithm and Its Architecture
5-5 Performance Comparisons
CHAPTER 6. SYSTOLIC ARRAY PROCESSORS OF RECURSIVE MORPHOLOGICAL OPERATIONS
6-1 The Union-Form Structuring Element Decomposition
6-2 Modular Systolic Realization
CHAPTER 7. SYSTOLIC ARRAY PROCESSORS OF FULL SEARCH BLOCK MATCHING ALGORITHM
7-1 Mapping the FBMA onto a DG
7-2 Mapping the DG onto Systolic Arrays
7-3 Shift Register Array and PE Designs
7-4 Performance Comparisons
CHAPTER 8. CONCLUSIONS
REFERENCES
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