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研究生:李裕能
研究生(外文):Yu-Neng Li
論文名稱:高性能微處理機之地板規劃與繞線
論文名稱(外文):Floorplan and Routing for A High Performance Microprocessor
指導教授:張明峰張明峰引用關係
指導教授(外文):Ming-Feng Chang
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:中文
論文頁數:52
中文關鍵詞:地板規劃繞線腳位配置全域訊號繞線
外文關鍵詞:floorplanroutingpin assignmentGSR ( global signal routing )
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隨著積體電路製程技術的進步,晶片內的電晶體個數及工作頻率快速的增加,電路的複雜性越來越高,電路的設計需由一個龐大的團隊來共同研發完成。一般來說,現行的晶片設計採用階層式的設計,將整個晶片切割成數個區塊來進行,當設計完成後再進行整合的工作。而設計流程通常是採用「瀑布式」模式,即當一個階段完成後,將此結果送到下個階段當輸入。如此的模式若沒有考慮到其對後段流程的影響,當後段設計碰到問題時,只好回到前面階段重新設計,如此將耗費許多時間在重複執行此流程。在本篇論文中,我們針對NSC98這顆高性能微處理機的頂層實體佈局提出一設計流程,此流程包括了地板規劃(floorplanning)、腳位配置(pin assignment)以及繞線(routing)三個步驟。由於NSC98有特殊的設計,並且晶片的面積非常地大,而無法使用Cadence的Preview/Silicon Ensemble來進行自動化佈局,所以我們針對我們的需求,自行發展程式來進行整個流程。我們在初步地板規劃完成後,進行地板規劃的評估,避免在腳位配置或繞線時,碰到錯誤而得重新地板規劃。最後我們完成了NSC98的頂層實體佈局,並且得到不錯的結果。

The rapid advance in VLSI technology results in an exponential increase in chip transistor counts and a significant increase in clock frequency. In general, large system design usually uses a hierarchical design approach, where the chip is divided into blocks. The blocks are developed separately and integrated after they are completed. A typical design flow can be depicted as a waterfall model, where a design stage is completed and the results are passed on to the next stage. The design of each stage can affect the quality of later stage designs. If there are problems unsolved in later stages, system redesign may be required for the early stages. In this thesis, we develop a design flow for the top level physical layout design of NSC98, including floorplanning, pin assignment and routing. In floorplanning design, we consider the factors that affect the performance of pin assignment and routing. In addition to using Cadence tools for floorplanning, we have developed pin assignment and routing CAD tools to complete our design. Finally we designed the top level physical layout of a high performance microprocessor NSC98 using the design flow.

中文摘要I
英文摘要II
誌 謝III
目 錄IV
表目錄VI
圖目錄VII
一、緒 論1
二、相關研究3
2.1地板規劃5
2.1.1演算法5
2.1.2地板規劃最佳化6
三、設計流程10
3.1模組實體佈局流程11
3.2頂層實體佈局整合流程(CADENCE)14
3.2.1地板規劃14
3.2.2腳位配置及繞線14
3.3我們所提出的頂層實體佈局流程(GSR AND M1žſ)15
3.3.1全域訊號繞線16
3.3.2實體佈局流程(GSR and M1-3)18
四、地板規劃20
4.1分析模組間連線情況24
4.2切割與擺放26
4.3地板規劃效能的評估27
4.3.1模組間的連線預估28
4.3.2檢查模組邊長29
4.3.3存在相鄰模組連線的匯流排(bus)數目29
4.3.4地板規劃效能評估的結果30
4.4訊號線分類30
4.5全域訊號繞線的腳位配置33
五、繞線37
5.1 M1-3繞線37
5.1.1架構37
5.1.2演算法38
六、實例設計結果40
七、結論與未來工作44
參考文獻45
中英對照表47
附錄AFLOORPLAN FILE及DEF49
FLOORPLAN FILE49
DEF51

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[2]陳宏章, “Clock and Power/Ground Distribution for Microprocessor”, 國立交通大學資訊工程研究所碩士論文, 1998.
[3]“Die Photo Gallery”, Micro Design Resource, 1998.
[4]M.Sarrafzadeh, C. K. Wong, An Inteoduction to VLSI Physical Design, The McGraw-Hill, 1996.
[5]Sadiq M. Sait, Habib Youssef, VLSI Physical Design Automation Theory and Practice, The McGraw-Hill, 1995.
[6]Lu Sha, “A Macro Cell Placement Algorithm Using Mathematical Programming Techniques”, Ph.D dissertation, Stanford University, March 1989.
[7]D.F. Wong and C.L. Liu, “An Optimal Algorithm for Floorplan Area Optimization”, Proc. 27th ACM/IEEE Design Automation Conf., pp.180-186, 1990.
[8]H Onodera, Y. Taniguchi, and K. Tamaru, “Branch-and-Bound Placement for Building Block Layout”, 1990 International Workshop on Layout Synthesis, 1990.
[9]G. Vijayan and R.S. Tsay, “Floorplanning by Topological Constraint Reduction”, 1990 IEEE International Conference on Computer-Aided Design, pp.106-109,1990.
[10]Partha S. Dasgupta, Susmita Sur-Kolay, and Bhargab B. Bhattacharya, “A Unified Approach to Topology Generation and Optimal Sizing of Floorplans”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Feb. 1997.
[11]Maurizio Rebaudengo and Matteo Sonza Reorda, “GALLO: A Genetic Algorithm for Floorplan Area Optimization”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Aug. 1996.
[12]K. H. Yeap and M. Sarrafzadeh, “ Sliceable floorplanning by graph dualization”, SIAM J. Discrete Math. , Vol. 8, pp.258-280, May. 1995.
[13]Weiping Shi, “A Fast Algorithm for Area Minimization of Slicing Floorplans”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, pp.1525-1532, Dec. 1996.
[14]Takashi Mitsuhashi, Takahiro Aokim Masami Murakata, and Kenji Yoshida, “Physical Design CAD in Deep Sub-micron Era”, IEEE Euro-DAC ’96 with EURO-VHDL ‘96., Jun. 1996.
[15]Takeo Hamada, Chung-Kuan Cheng and Paul M. Chau , “A Wire Length Estimation Technique Utilizing Neighborhood Density Equations”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, pp.912-921, Aug. 1996.
[16]Danny Z. Chen and Xiaono(Sharon) Hu, “Efficient Approximation Algorithms for Floorplan Area Minimization”, 33rd Design Automation Conference, 1996.
[17]許俊銘、李杰原、蔡慶宏, Cell-Based Physical Design and Verification Training Manual, CIC, July 1998.
[18]Sechen, C., “Chip-Planning, Placement, and Global Routing Program: User’s Guide for Version 3.2, Release 2”, unpublished paper, 1986.
[19]Hsu, C. P., “APLS2: A Standard Cell Layout System for Double-layer Metal Technology”, Design Automation Conference IEEE/ACM, 1985.

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