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研究生:許芷瑋
研究生(外文):Chih-Wei Hsu
論文名稱:基於指令長度預測的高頻寬多指令擷取
論文名稱(外文):High-Bandwidth Multiple Instruction Fetching Based on Instruction Length Prediction
指導教授:鍾崇斌
指導教授(外文):Chung-Ping Chung
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:英文
論文頁數:55
中文關鍵詞:指令擷取高頻寬長度預測
外文關鍵詞:Instruction FetchingHigh-BandwidthLength Prediction
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指令擷取是微處理器管線中的第一級,因此對於微處理器尤其是超純量微處理器的效能有相當大的影響。在超純量微處理器中,指令擷取器每一週期必須提供數個指令給解碼器。然而在x86架構下,由於不定長度指令使得在一個時脈週期內要擷取多個指令相當困難。
在此論文中,我們提出指令識別器的方法,此方法藉由預測指令長度與利用表格儲存指令指標來同時提供數個指令給指令擷取器。突破過去達到高超純量程度(superscalar degree)的困難,加速了指令擷取的效能。
模擬結果建議在效能/花費的考量下,64個表格條目(entry)為適當的選擇。模擬結果也顯示表格的條目越少,預測的方法越重要。另外,模擬和合成(synthesis)的結果顯示我們提出的架構在0.6微米(micron)的製程下,可以達到200MHz。

Because instruction fetch is the first pipeline stage in a microprocessor, it significantly influences the performance of a microprocessor, especially superscalar microprocessor. In a superscalar microprocessor, the instruction fetcher must provide multiple instructions to the decoders each cycle. However, in the x86 architecture, the variable-length instruction makes fetching multiple instructions in a clock cycle difficult.
In this thesis, we propose an approach, Instruction Identifier, which can easily provide multiple instruction pointers to the fetcher simultaneously by means of predicting instruction length and storing the instruction pointers to the table. It breaks the difficulty of achieving high superscalar degree (>3) and speeds up the instruction fetching performance.
Simulation results suggest that 64-entry table is the proper choice under performance/cost consideration. And simulation results also show that the more the number of entries in the table decreases, the more the prediction scheme becomes important. Besides, simulation and synthesis results show that our design can attain 200 MHz in 0.6-micron process technology.

Chapter 1 Introduction
Chapter 2 Survey
2.1 Study of Instruction Fetch Model
2.2 Survey of x86 Microprocessors
2.2.1 Intel Pentium
2.2.2 Intel Pentium with MMX Technology
2.2.3 AMD K5
2.2.4 AMD K6
2.2.5 Intel Pentium Pro / Pentium II
2.3 Review of Instruction Fetch Mechanism
2.3.1 Essence of Instruction Fetch Mechanism
2.3.2 Comparison of the Instruction Fetch Mechanisms
Chapter 3 Instruction Identifier
3.1 Purpose of Instruction Identifier
3.2 Operations of Instruction Identifier
3.3 Architecture of Instruction Identifier
Chapter 4 System Performance Study
4.1 Simulation Environment
4.2 Performance Evaluations and Analyses
4.2.1 Prediction Scheme Analysis
4.2.2 Hardware Cost Analysis
4.2.3 Number of Entries Analysis
4.2.4 Instruction Cache Line Size Analysis
4.3 Delay Time Evaluations
Chapter 5 Conclusions

[1] J.C. Chiu, J.N. Yang, R.M. Shiu, C.P. Chung, “A proposed
Fetch Rule Model for Fetching Multiple X86 Instructions,”
Proceedings of 1998 International Conference on Computer
Systems Technology for Industrial Applications, pp. 31-36.
[2] B.Case, “Intel Reveals Pentium Implementation Details,”
Microprocessor Report, Vol.7, No.4, March 29, 1993
[3] Intel Corporation, Pentium Processor Family Developer’s
Manual, 1997
[4] M.Slater, “Intel’s Long-Awaited P55C Disclosed,”
Microprocessor Report, Vol.10, No.14, October 28, 1996
[5] D.Christie, “Developing the AMD-K5 Architecture,” IEEE
Micro, Vol.16, Iss.2, pp.16-27, April 1996
[6] M.Slater, “AMD’s K5 Designed to Outrun Pentium,”
Microprocessor Report, Vol.8, No.14, October 24, 1994
[7] AMD Corporation, AMD 5K86 Processor Technical Reference
Manual, 1996
[8] M.Johnson, Superscalar Microprocessor Design, Prentice
Hall, 1991
[9] L.Gwennap, “Nx686 Goes Toe-o-Toe with Pentium Pro,”
Microprocessor Report, Vol.9, No.14, October 23, 1995
[10] M.Slater, “K6 to Boost AMD’s Position in 1997,”
Microprocessor Report, Vol.10, No.14, October 28, 1996
[11] AMD Corporation, AMD-K6 MMX Enhanced Processor Datasheet,
1997
[12] L.Gwennap, “Intel’s P6 Uses Decoupled Superscalar
Design,” Microprocessor Report, Vol.9, No.2, February 16,
1995
[13] Intel Corporation, Pentium Pro Family Developer’s Manual
Vol.1 Specifications, 1996
[14] Intel Corporation, Pentium II Processor Developer’s
Manual, October 1997
[15] J.Y. Wang, “Design of an Instruction Fetcher with Address
Queue for x86 Superscalar Microprocessors,” M.S. thesis,
Department of Computer Science and Information
Engineering, National Chiao-Tung University, 1998
[16] Intel Corporation, Pentium Pro Family Developer’s Manual
Vol.3 Operating System Writer’s Guide, December 1995

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