臺灣博碩士論文加值系統

本論文之目的是針對多晶片模組發展一套有效率之可測試設計及測試策略。在互補式金屬氧化半導體多晶片模組之內建式電流測試方法中，適當地分割電路為多個模組以便加入內建式電流感應器是權衡測試成本及測試正確性的一個重要關鍵。目前多數的電路分割方法是以統計分析的方式找出一個固定的臨界值來決定模組的大小。這些方法的缺點是缺乏彈性，因為電流測試方法是以測量具類比性質的電流做為判斷電路錯誤之依據而非以測量數位信號之方式來判斷電路之錯誤。我們提出了一個基於模糊推理的方法，以提供一個具有彈性的臨界值來決定內建式電流測試方法中電路模組的大小。實驗結果顯示我們所提出的方法的確能在內建式電流測試之電路分割設計空間中找出適當的模組大小。其次，我們也發展出一個簡單而有效的模式來預估部份可測試多晶片模組之錯誤涵蓋率。這個模式能夠充分反應多晶片模組中錯誤涵蓋率、測試方法，以及可測試晶片之比例及其分佈之關係。實驗結果顯示我們所提出的模式可以有效地預估部份可測試多晶片模組之錯誤涵蓋率，其誤差範圍在5%內。此模式可以協助多晶片模組設計人員有效地規劃可測試晶片之使用。此外，我們也提出了一個基於多頻率掃描之測試方法來偵測多晶片模組之靜態及動態錯誤。我們藉由變更部分邊界掃描細胞之設計，使同樣的邊界掃描細胞不但可以用在晶片階層之測試上，同時也可以用於模組階層之測試上。實驗結果顯示因加入測試電路所造成之面積多支及延遲時間可以減少。

The goal of this thesis is to develop efficient DFT (design for
testability) and test strategies for MCMs (multichip modules) during their production and test processes. In CMOS MCMs, partitioning a circuit into modules before using a separate
built-in current sensor for each module is key to balancing between test cost and test correctness of built-in current test. Most partitioning methods use statistic analysis to find a fixed threshold and then to determine the size of a module. These methods are rigid and inflexible since IDDQ (quiescent power supply current) testing requires the measurement of an
analog quantity rather than a digital signal. We propose a fuzzy-based approach which provides a soft threshold to determine the module size for BICT partitioning. Experimental results show that our design approach provides a feasible way to exploit the design space of BICT partitioning. A simple and
efficient model for designers to estimate the fault coverage of a partially testable MCM is also derived. This model reflects the relationship between fault coverage, test methodology, and the ratio and distribution of DFT dies (dies with testability features) in an MCM. Experimental results show that our model can efficiently predict the actual fault coverage of a
partially testable MCM with less than 5% deviation. It indeed facilitates the designers to plan the use of DFT dies in MCMs in an efficient way.In addition, we propose a multifrequency scan based MCM test method which is closely associated with the
mixed technologies of MCMs. This method can detect both static and dynamic faults. Furthermore, by introducing modified boundary scan cells, the same boundary scan cells which are used in chip level test can also be used in module level test. Experimental results show that the area overhead as well as the extra delay due to the addition of test circuits can be reduced.

封面
Abstract(in Chinese)
Abstract(in English)
Acknowledgements(in Chinese)
Table of Contents
List of Figures
List of Tables
1 Introduction
2 Fuzzy-based Circuit Partitioning in Built-in Current Testing for CMOS MCMs
2.1 Introdution
2.2 Preliminaries
2.3 Design Approach
2.4 Discussion
2.5 Experimental Results
3 Fault Coverage and Defect Level Estimation Models for Partially Testable MCMs
3.1 Introcdution
3.2 Preliminaries
3.3 Fault coverage Estimation Model
3.4 Gemetic Algorithm-based DFT Dies Deplyment Automation
3.5 Defect Level Estimation Models
3.6 Experiments
4 Built-in Self-Test Multichip Modules with Multifrequency Scan Strategy
4.1 Introduction
4.2 Design Approach and System Architecture
4.3 Test Procedures
4.4 Design Example
4.5 Experiments and Evaluation
5 Conclusions and Future Work
5.1 Conclusions
5.2 Future work
Bibliography

[1]. Kuen-Jong Lee and Melvin A. Breuer, "Design and Test Rules for CMOS Circuits to Facilitate IDDQ Testing of Bridging Faults,"IEEE Trans. Computer-Aided Design}, Vol. 11, No. 5, pp. 659-670, May 1992.
[2]. W. Mao, R. K. Gulati, D. K. Goel, and M. D. Ciletti, "QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults," Proceedings of the IEEE Int''l Conf. on Computer-Aided Design, Nov.1990, pp. 280-283.
[3]. Yashwant K. Malaiya, Anura P. Jayasumana, Qiao Tong, and Sankaran M. Menon, "Enhancement of Resolution in Supply Current Based Testing for Large ICs," Proceedings of the IEEE VLSI Test Symposium, Apr. 1991, pp. 291-296.
[4]. Steven D. McEuen, "Reliability Benefits of IDDQ," Journal of Electronic Testing: Theory and Applications, 3, pp. 327-335, Sep. 1992.
[5]. Michael J. Riezenman, "Test and Measurement," IEEE Spectrum, pp. 52-55, Jan. 1995.
[6]. David M. Wu, newblock "Can IDDQ Test Replace Conventional Stuck-Fault Test?" Proceedings of the IEEE Custom Integrated Circuit Conf., May 1991, pp. 13.2.1-13.2.4.
[7]. Wojciech Maly and Marek Patyra, "Built-in Current Testing,"
IEEE Journal of Solid-State Circuits, pp. 425-428, Mar. 1992.
[8]. Wojciech Maly and Marek Patyra, "Design of ICs Applying Built-in Current Testing,"Journal of Electronic Testing: Theory and Applications, 3, pp. 397-406, Sep. 1992.
[9]. Carol Q. Tong, Mindy Wen, and Shyang-Tai Su,"IDDQ Testing in Low Power Supply CMOS Circuits, "Proceedings of the IEEE Custom Integrated Circuit Conf., Sep. 1996, pp. 22.1.1-22.2.4.
[10]. Anne E. Gattiker and Wojciech Maly, "Current Signatures,"
Proceedings of the IEEE VLSI Test Symposium, pp. 112-117, Apr. 1996.
[11]. Bryan Preas and Michael Lorenzetti (eds.), Physical Design Automation of VLSI Systems, The Benjamin/Cummings Publishing Company, Inc., 1988.
[12]. Naveed Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers, 1995.
[13]. F. R. Biglari and X. D. Fang,"Real-Time Fuzzy Logic Control for Maximizing the Tool Life of Small-Diameter Drills,"
Fuzzy Sets and Systems}, 72, pp. 91-101, Mar. 1995.
[14]. R. R. Yanger and D. P. Filev, Essentials of Fuzzy Modeling and Control}, John Wiley & Sons, 1994.
[15]. A. Ferre and J. Figueras, On Estimating Bounds of Quiescent Current for IDDQ Testing, Proceedings of the IEEE VLSI Test Symposium, Apr. 1996, pp. 106-111.
[16]. D. Josephson, M. Storey, and D. Dixon, Microprocessor IDDQ Testing: a Case Study, IEEE Design and Test of Computers, [17]. C. Thibeault, A Novel Probabilistic Approach for IC Diagnosis based on Differential Quiescent Current Signatures, Proceedings of the IEEE VLSI Test Symposium, Apr. 1997, pp. 80-84.
[18]. Terry Sincich, Statistics by Example, Macmillan Publishing Company, 1993.
[19]. M. Dalpasso, M. Favalli, and P. Olivo. "IDDQ Test Invalidation by Break Faults," Electronics Letters, Vol. 32, pp. 994-995, May 1996.
[20]. James J. Licari, Multichip Module Design, Fabrication, and Testing, McGraw-Hill, 1994.
[21]. Steven D. Millman
"Improving Quality: Yield vs. Test Coverage," Proceedings of the Int''l Conf. on Wafer Scale Integration}, Jan. 1993, pp. 279-288.
[22]. John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, 2nd Ed., Morgan Kaufmann Publishers, Inc., 1996.
[23]. Gordon D. Robinson and John G. Deshayes, "Interconnect Testing of Boards with Partial Boundary Scan," Proceedings of the Int''l Test Conf., Sep. 1990, pp. 572-581.
[24]. Sadiq M. Sait and Habib Youssfe, VLSI Physical Design Automation, McGRAW-HILL, 1995.
[25]. B. B. Prahlada Rao, L. M. Patnaik, and R. C. Hansdah, "A Genetic Algorithm for Channel Routing Using Inter-Cluster Mutation," Proceedings of the First IEEE Conf. on Evolutionary Computation, June 1994, pp. 79-103.
[26]. Jose'' L. Ribeiro Filho, and Philip C. Treleaven, "Genetic-Algorithm Programming Environments,", Vol. 27, Iss. 6, pp. 28-43, June 1994.
[27]. L. Davis, "Applying Adaptive Algorithms to Epistatic Domains," Proceedings of the Int''l Joint Conf. on Artificial Intelligence}, 1985, pp. 162-164.
[28]. Zbigniew Michalewicz, Genetic Algorithms + Data Structure = Evolution Programs}, Springer-Verlag, 1994.
[29]. F. Brglez and H. Fuijwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," Proceedings of the Int''l Test Conf., Oct. 1985, pp. 785-794.
[30]. F. Corsi, D. Del Console, and C. Marzocca, "Defect Level for Non-Equiprobable Faults in Digital ICs," Electronics Letters, Vol. 29, No. 8, pp. 653-654, Apr. 1993.
[31]. A. D. Singh and C. M. Krishna, "On Optimizing VLSI Testing for Product Quality Using Die-Yield Prediction," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 5, pp. 695-709, May 1993.
[32]. T. W. Williams and N. C. Brown, "Defect Level as a Function of Fault Coverage," IEEE Trans. Computers, Vol. C-30, No. 12, pp. 987-988, Dec. 1981.
[33]. F. Corsi, S. Martino, and T. W. Williams, "Defect Level as a Function of Fault Coverage and Yield," Proceedings of the European Test Conf., Apr. 1993, pp. 507-508.
[34]. J. T. Sousa, F. M. Goncalves, J. P. Teixeira, and T. W. Williams, "Fault Modeling and Defect Level Projections in Digital ICs," Proceedings of the European Design and Test Conf., Mar. 1994, pp. 436-442.
[35]. J. T. Sousa and J. P. Teixeira, "Defect Level Estimation for Digital ICs," Proceedings of the Int''l Workshop on Defect and Fault Tolerance in VLSI Systems, Nov.
1992, pp. 32-41.
[36]. James A. Cunningham,
"The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing," IEEE Trans. Semiconductor Manufacturing, Vol. 3, No. 2, pp. 60-71, May 1990.
[37]. Daryl Ann Doane and Paul D. Franzon, Multichip Module Technologies and Alternatives, Van Nostrand Reinhold, 1993.
[38]. J. K. Hagge and R. J. Wagner, "High Yield Assembly of Multichip Modules through Known-Good ICs and Effective Test Strategies," Proceedings of the IEEE, vol. 80, No. 12, pp. 59-66, Dec. 1992.
[39]. Yervant Zorian, "A Structured Testability Approach for Multi-Chip Module Based on BIST and Boundary-Scan," IEEE Trans. Components, Packaging, and Manufacturing Technology, Part B, Vol. 17, No. 3, pp. 283-290, Aug. 1994.
[40]. Andrew Flint, "Testing Multichip Modules," IEEE Spectrum, pp. 59-62, Mar. 1994.
[41]. Magdy S. Abadir, Ashish R. Parikh, Peter A. Sandborn, and Ken Drake, "Analyzing Multichip Module Testing Strategies," IEEE Design and Test, pp. 40-51, Spring 1994.
[42]. William M. Siu, "MCM and Monolithic VLSI Perspectives on Dependencies, Integration, Performance and Economics," Proceedings of the IEEE Multichip Module Conf., Oct. 1992, pp. 4-7.
[43]. Anne E. Gattiker, Wojciech Maly, and Michael E. Thomas, "Are There Any Alternatives to Known Good Die?" Proceedings of the IEEE Multichip Module Conf.,
Oct. 1994, pp. 102-107.
[44]. W. Maly, D. Feltham, A. Gattiker, M. Hobaugh, K. Backus, and M. Thomas, "Multi-Chip Module Smart Substrate System," IEEE Design and Test, pp. 64-73, Spring 1994.
[45]. Marcelo Lubazewski, Meryem Marzouki, and Mohamed Hedi Touati, "A Pragmatic Test and Diagnosis Methodology for Partially Testable MCMs," Proceedings of the IEEE Multichip Module Conf., Oct. 1994, pp. 108-113.
[46]. Jean-Pierre Wyss, Claus Habiger, Etienne Hirt, and Gerhard Troster, "DFT Technique for First-Time Right MCMs- Exemplified by a Pentium MCM System," Proceedings of the Int''l Conf. on Multichip Modules and High Density Packaging, Apr. 1998, pp. 190-195.
[47]. Tadashi Kimura, Osamu Okuda, Haruo Ishikawa, and Yoshinori Suzuki, "Bare Chip Stacking Structure for MCM Production," Proceedings of the Int''l Conf. on Multichip Modules and High Density Packaging, Apr. 1998, pp. 303-307.
[48]. Kevin T. Kornegay and Kaushik Roy, "Structured Test Methodologies and Test Economics for Multichip Modules," IEEE Trans. Components, Packaging, and Manufacturing Technology, Part B, Vol. 19, No. 1, pp. 195-202, Feb. 1996.
[49]. Chih-Ang Chen and Sandeep K. Gupta, "BIST/DFT for performance Testing of Bare Dies and MCMs," Conf. Proceedings Combined Volumes Electro Int''l, May 1994, pp. 803-812.
[50]. David C. Keezer, "Fault Isolation and Performance Characterization of High Speed Digital Multichip Modules," IEEE Trans. Components, Packaging, and Manufacturing Technology, Part B, Vol. 18, No. 4, pp. 614-619, Nov. 1995.
[51]. David Karpenske and Chris Talbot, "Testing and Diagnosis of Multichip Modules," Proceedings of the Solid State Technology, June 1991, pp. 24-26.
[52]. Benoit Nadeau-Dostie and Dwayne Burek, "ScanBist: A Multifrequency Test Method," IEEE Design and Test, pp. 7-16, Spring 1994.
[53]. Colin M. Maunder and Rodham E. Tullos, The Test Access Port and Boundary-Scan Architecture, IEEE Computer Society Press Tutorial, 1990.
[54]. Kenneth E. Posse, "A Design-for-Testability Architecture for Multichip Modules," Proceedings of the Int''l Test Conf., July 1991, pp. 113-121.
[55]. Ting-Ting Y. Lin and Huoy-Yu Liou, "Built-in Test Multichip Modules with Pipelined Test Strategy," IEEE Design and Test, pp. 38-50, Fall 1993.
[56]. C. Dislis, A. F. Alani, and I. P. Jalowiecki, "A Framework for the Management of MCM Test Strategies," Proceedings of the Int''l Conf. on Multichip Modules, Apr. 1997, pp. 272-277.
[57]. N. Park, F. Lombardi, and Sungsoo Kim, "Modeling Quality Reduction of Multichip Module Systems due to Uneven Fault-Coverage and Imperfect Diagnosis," Proceedings of the Int''l Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 1996, pp. 168-176.
[58]. Daeje Chin, "Executing System on a Chip: Requirements for a Successful SOC
Implementation," Proceedings of the Electron Devices Meeting, Dec. 1998, pp. 3-8.
[59]. Earl E. Swartzlander, Jr., "VLSI, MCM, and WSI: A Design Comparison," IEEE Design and Test of Computers, pp. 28-34, Summer 1998.
[60]. H. De Man, "Future Systems-on-a-Chip: Impact on Engineering Education," Proceedings of the VLSI''98: System Level Design, Apr. 1998, pp. 78-83.
[61]. Kamalesh Ruparel, "SOC Test: The Devil is in the Details of Integration/Implementation," Proceedings of the Int''l Test Conf., Oct. 1998, pp. 1143-1143.
[62]. Rochit Rajsuman, "Design-for-Iddq-Testing for Embedded Cores Based System-on-a-Chip," Proceedings of the IEEE Int''l Workshop on IDDQ Testing, Nov. 1998, pp. 69-73.