在模擬以硬體規格描述語言（HDL）寫成的設計時，量測其驗證涵蓋率能提供一個模擬完整性的量化分析。同時，藉由觀察程式碼在模擬中執行的情形，也能讓作驗證的工程師找出哪些部分的程式碼尚未被測試，因而能集中心思在這些地方。在這篇論文中，我們提出一種新的量測驗證涵蓋率的方法。這方法是架構在訊號變化的紀錄檔案（VCD）上，而這些檔案在模擬執行時只需增加些許的計算負荷即可產生。對於各種不同的涵蓋率分析，我們都能很容易地由對同一份記錄檔所做的統計資料中推導出來。因而這方法能夠很快地在不同的涵蓋率分析報告之間轉換，而不必一再地重新執行冗長的模擬。如果使用者只需要部分的涵蓋率分析報告，我們也只需從記錄檔中取部分資料即可，如此便可以減低分析過程的複雜性。更重要的是，若是使用這個方法，使用者不需要額外一套昂貴的模擬器許可（Simulator License），就可以做涵蓋率分析。最後，從幾個實際的電路設計所做的實驗中，我們確實得到了不錯的結果。

While simulating the HDL (hardware description language) designs, the verification coverage measurement can provide a quantitative analysis of the simulation completeness. By monitoring the execution of the HDL code during simulation, the verification engineers can also identify the part of code which has not been tested so that they can focus their efforts on those areas. In this thesis, we propose a novel approach for verification coverage measurement based on the value change dump (VCD) files produced by the simulator with little computation overhead. For varieties of coverage metrics, the coverage report can be easily generated from the same execution statistics measured from the dumpfiles. Therefore, it provides the capability to switch between different coverage reports very fast without re-running the long simulation again and again. If only partial coverage report is required, we can retrieve only partial data from the dumpfile so that the complexity of the process can be reduced. More importantly, the users do not need an extra expensive simulator license to conduct the coverage analysis. Conducting some experiments on real examples, it shows very promising results.

Contents
摘要i
ABSTRACTii
ACKNOWLEDGEMENTSiii
CONTENTSiv
LIST OF TABLESvi
LIST OF FIGURESvii
Chapter 1INTRODUCTION……………………………………1
Chapter 2BACKGROUND……………………………………4
2.1 Type of Coverage…………………………………4
2.2 Current Approaches of Measuring Coverage………9
Chapter 3Dumpfile-Based Coverage Analysis……………………11
3.1 Value Change Dump File (VCD)……………………11
3.2 HDL Modeling……………………………………12
3.3 Dumpfiled-based Coverage Analysis(DUCA)………15
3.3.1 Variable Selection…………………………16
3.3.2 Running Analysis……………………………16
3.3.3 Coverage Report……………………………21
3.3.4 DUCA Algorithm……………………………22
Chapter 4Implementation………………………………………24
4.1Parse HDL Code…………………………25
4.2Create Event Graph………………………25
4.3Variable Selection…………………………28
4.4Parse Dumpfile……………………………29
4.5Traverse Dumpfile…………………………29
4.6Post-processing……………………………30
Chapter 5Experimental Results…………………………………31
Chapter 6Conclusion……………………………………………34
Chapter 7Future Work…………………………………………35
References ………………………………………………………36

References
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[2] VIS (Verification Interacting with Synthesis) , Berkeley CAD Group. ( http://www-cad.eecs.berkeley.edu/~vis )
[3] Tsu-Hua Wang and Chong Guan Tan, "Practical Code Coverage for Verilog", Int'l Verilog HDL Conference, 1995.
[4] Aarti Gupta, Sharad Malik, and Pranav Ashar, "Toward Formalizing a Validation Methodology Using Simulation Coverage", 34th DAC, 1997.
[5] Dean Drako and Paul Cohen, "HDL Verification Coverage", Integrated Systems Design Magazine, June 1998.
( http://www.isdmag.com/Editorial/1998/CodeCoverage9806.html )
[6] CoverMeter, Advanced Technology Center.( http://www.covermeter.com )
[7] CoverScan, Design Acceleration Incorporation. ( http://www.designacc.com/products/coverscan/index.html )
[8] HDLScore, Summit Design Incorporation. ( http://www.summit-design.com/products/hdlscore.html )
[9] Cadence Reference Manuals.
[10] Robert S. French, Monica S. Lam, Jeremy R. Levitt, and Kunle Olukotun, "A General Method for Compiling Event-Driven Simulations", 32nd DAC, 1995.
[11] Richard C. Ho and Mark A. Horowitz, "Validation Coverage Analysis for Complex Digital Designs", ICCAD, 1996.