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研究生:彭文孝
研究生(外文):Wen-Shiaw Peng
論文名稱:應用於二維可分離式離散小波轉換之高效能演算法和架構設計
論文名稱(外文):An Efficient Algorithm and Architecture Design For Two- Dimension Separable Discrete Wavelet Transform
指導教授:李鎮宜
指導教授(外文):Chen-Yi Lee
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:英文
論文頁數:135
中文關鍵詞:離散小波轉換二維可分離式離散小波轉換
外文關鍵詞:Discrete Wavelet TransformTwo- Dimension Separable Discrete Wavelet Transform
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近幾年來,離散小波轉換已成為一個強大的工具並且被應用在不同的領域諸如:影像的壓縮和分析﹑材質的辨別﹑碎形分析和圖案辨認等等。由於在時域和頻譜域上的局部化特性使得小波轉換在移除訊號相關性的能力上優於已往的離散餘弦轉換和傅立葉轉換。同時,以小波轉換為依據的影像壓縮技術其效能已被證實是優於用離散餘弦轉換的,尤其是在相當低的位元率情況下。基於這些優點,即將到來的JPEG 2000和MPEG 4國際標準已採納了離散小波轉換的使用。在這篇論文中,我們將專注在小波轉換於靜態影像壓縮的應用上。我們將簡單的介紹小波轉換的原理和仔細的探討用於二維小波轉換的 Circular-Parallel 架構。除此之外,一些以小波轉換為依據的相關影像壓縮演算法也將在本篇論文被提及。從這些演算法我們可以更清楚的瞭解離散小波轉換模組在整個系統所扮演的角色。這將有助於我們去設計離散小波轉換模組的輸入輸出使得將來此模組能夠不必耗費太多的努力就能和其他系統模組順利的連接運作。我們提出架構的關鍵點在於利用不同階層濾波段係數的依存關係,進而利用此關係做係數運算的排序。和過去被提出的架構和演算法比較起來,我們的架構能夠有較簡單的記憶體輸入輸出介面和較低的硬體代價。而且此架構能適合各種即時的影像應用以列接著一列的方式來完成二維的離散小波轉換運算。
在TSMC SPTM 0.6um 的製程下,我們用COMPASSTM 0.6um高性能的標準元件(Standard Cells)來實現此架構。這顆晶片整合了大約160k個電晶體於5.4mm x 5.3mm的矽面積上並且能夠處理高達8個濾波器係數和12.5Mhz的輸入取樣率。此一處理速度能夠滿足目前許多的影像和動態視訊會議的編碼應用。
In recent years, the Discrete Wavelet Transform (DWT) has become a powerful tool in many areas, such as image compression and analysis, texture discrimination, fractal analysis, pattern recognition and so on. Due to the localization property both in time and frequency domain, wavelet transform is more efficient than Short Time Fourier Transform (STFT) or Discrete Cosine Transform (DCT) in de-correlating the time domain signal correlation. Also, it has been proved that the wavelet based image compression scheme has better performance than that with DCT based especially in very low bit rate. Due to these advantages, the DWT has been included in the coming JPEG2000 and MPEG4 standards. In this thesis, we focus on the still image compression application of wavelet transform. We will give a brief introduction of wavelet transform and describe the proposed Circular-Parallel architecture (CPA) for 2-D DWT computation in detail. In addition, some wavelet based coding algorithms are presented in this thesis. From these coding algorithms, we can clearly understand the role of DWT module in the overall system. This helps us to design the I/O of the DWT module such that it can incorporate with the other modules in the system without too much additional effort. The key point of the proposed architecture is to exploit the dependence of different filter bank coefficients and further to schedule the computation order of these coefficients based on the dependence. As compared with some previously proposed architectures, our architecture has simpler memory I/O interface and lower hardware cost. And it can process the 2-D DWT in line by line fashion that is suitable for many real-time image coding applications.
Based on TSMC SPTM 0.6um process technology, we use COMPASSTM 0.6um high performance cell library to implement the proposed CPA architecture. The chip integrates about 44k gates in 5.4mm x 5.3mm silicon area with the capability to process 8-tap filter and 12.5 MHz input sample rate that can meet many image and videoconference real-time applications.
Contents
CHAPTER 1 INTRODUCTION1
1.1 Motivation1
1.2 Basic idea of wavelet transform4
1.4 Organization of the thesis9
CHAPTER 2 THE FUNDAMENTAL THEORY OF DISCRETE WAVELET TRANSFORM11
2.1 Wavelet Theory- Multiresolution approximation of L2 ( R )11
Scaling function11
Wavelet function14
Reconstruction from an Orthogonal Wavelet Representation17
The Orthogonal Wavelet Representation of 2-D signals18
2.2 Simulation of wavelet theory20
One dimension case20
Two dimensions case22
CHAPTER 3 DWT MODULE IN WAVELET BASED STILL IMAGE COMPRESSION SYSTEM25
3.1 Introduction25
3.2 The wavelet based coding algorithm27
3.2.1 The embedded zerotree wavelet coding algorithm27
3.2.2 The lined based and reduced memory coding algorithm34
3.3 System requirements of the DWT module37
CHAPTER 4 1-D & 2-D DWT ALGORITHM AND ARCHITECTURE DESIGN38
4.1 Introduction to Multirate-Systems38
4.1.1 Basic Multirate operations and building blocks39
4.1.2 Noble Identities and Polyphase representation42
4.2 Related Work45
4.2.1 1-D DWT Algorithms and Architectures46
4.2.2 2-D DWT Algorithms and Architectures63
4.3 THE PROPOSED CIRCULAR-PARALLEL ARCHITECTURE69
4.3.1 Recursive Pyramid Algorithm based 2-D DWT scheduling70
4.3.2 The Overall Structure of Circular-Parallel Architecture74
4.3.3 Row Unit83
4.3.4 Column Unit84
4.3.5 Register Bank Unit85
4.3.6 Wordlength Simulation of Circular-Parallel Architecture87
4.4 Architecture Performance Comparisons90
CHAPTER 5 CIRCUIT SIMULATION AND DESIGN FLOW94
5.1 Circuit design consideration94
5.1.1 Bi-directional I/O pin94
5.1.2 Clock skew and distribution96
5.1.3 Power Consideration98
5.2 Design flow and methodology100
5.3 Chip features103
5.4 Post-Layout Simulation104
CHAPTER 6 CONCLUSIONS AND FUTURE WORK106
6.1 Conclusion106
6.2 Future work and related research topics108
Appendix I. C++ Program of Circular-Parallel Architecture..................................115
Appendix II. Verilog Description..............................................................................126
Appendix III. Interconnection diagram among different modules within the DWT
Processor....................................................................................................................133
Appendix IV. Chip pins assignment..........................................................................13
Bibliography
[1] S.Mallat., “A theory for Multiresolution Signal Decomposition: the Wavelet Representation,” IEEE Trans. On Pattern Analysis and Machine Intell., vol.11, pp.674-693, July 1989.
[2] G. Knowles, ”VLSI architectures for the discrete wavelet transform,” Electron. Lett., vol. 26, no. 15, pp.1184-1185, July 1990.
[3] A. S. Lewis and G. Knowles, ”VLSI architecture for 2-D daubechies wavelet transform without multipliers,” Electron. Letters, vol. 27, no. 2, pp.171-173, Jan 1991.
[4] K.K Parhi, ”Systematic Synthesis of DSP Data Format Converters Using Life-Time Analysis and Fordward-Backward Register Allocation,” IEEE Trans. On Circuits and Systems-II:Anslong and Digital Signal Processing, vol. 39, no. 7, July 1992.
[5] K. K. Parhi and T. Nishitani, “VLSI architectures for discrete wavelet transforms,” IEEE Trans. VLSI Syst., vol . 1, pp. 191-202, 1993
[6] M. Vishwanath, ”The recursive pyramid algorithm for discrete wavelet transform,” IEEE Trans. Signal Processings., vol .42, no. 3, pp.673-676, Mar. 1994.
[7] M.Vishwanth, R.Owesm, and M.J. Irwin, ”VLSI architectures for the discrete wavelets transform,” IEEE Trans. Circuits and System II, Analog and Digital Signal Processing, vol. 42, no. 6,pp. 305-316, May 1995.
[8] C. Chakrabarti, M. Vishwanth, “Efficient realizations of the discrete and contineous wavelets transforms: from single chip implementations to mappings on SIMD array computers,” IEEE Trans. Signal Processing, vol. 43, no.3, pp.759-771, Mar 1995.
[9] C. Chakrabarti, M. Vishwanth, R.Owens, ”Architecture for wavelets transforms: a survey,” Journal of VLSI Signal Processing, vol. 14, no. 2, pp.171-192, Nov. 1996.
[10] S. Mallat, a Wavelet tour of signal processing, Academic Press, 1998
[11] “An Introduction to Wavelets”,
http://www.amara.com/IEEEwave/IEEEwavlet.html
[12] J.M. Shapiro, “Embedded image coding using zerotree of wavelet coefficients,” IEEE Trans. Signal Processing, vol. 41, pp. 3445-3462, Dec. 1993.
[13] A.Said and A. Pearlman, “A New, Fast, and Efficient Image Codec Based on set Partition in Hierarchical Trees,” IEEE Trans. Circuits and System For Video Technology, vol. 6, pp. 243-250, June 1996
[14] Chrysafis. C and Ortega. A, “Line based reduced memory, wavelet image compression,” IEEE DCC’98 Proceedings, pp. 398-407, April 1998.
[15] Z. Xiong and K. Ramchandran and M. T. Orchard, “Space-frequency Quantization for Wavelet Image Coding,” IEEE Trans. Image Processing, vol. 6, pp.677-693, May 1997.
[16] Chrysafis. C and Ortega.A, “Efficient Context-based Entropy Coding for Lossy Wavelet Image Compression,” in Proc. IEEE Data Compression Conference, pp.241-250, IEEE Computer Society Press, Los Alamitos, California, 1997.
[17] Weinberger.M.J. ,Seroussi.G and Sapiro.G, “LOCO-I: A Low Complexity, Context-Based, Lossless Image Compression Algorithm,” IEEE DCC’96 Proceedings, pp. 140-149, April 1996.
[18] P.P. Vaidyanathan, “MULTIRATE SYSTEMS AND FILTER BANKS,” Englewood Cliffs, Prentice Hall, New Jersey, 1993
[19] A.V. Oppenheim, Ronald W.Schafer, “DISCRETE TIME SIGNAL PROCESSING,” Englewood Cliffs, Prentice Hall, New Jersey, 1989.
[20] M. Vishwanath, “The recursive pyramid algorithm for the discrete wavelet trabsfrom,” IEEE Trans. on Signal Processing, vol.42, no. 3, pp673-676, Mar. 1994
[21] Sung Bum Pan and Rae-Hong Park, “NEW SYSTOLIC ARRAYS FOR COMPUTATION OF THE 1-D DISCRETE WAVELET TRANSFORM”, IEEE Acoustics, Speech, and Signal Processing Conference, vol. 5, pp. 4113-4116, Apr. 1997
[22] K.K. Parhi, “Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation,” IEEE Trans. Circuits Syst-II, vol. 39, pp. 423-440, July 1992.
[23] K.K. Parhi, “Video data format convetors using minimum number of registers,” IEEE Trans. Circuits Syst. Video Technol., vol. 2, pp.255-267, June 1992.
[24] Aleksander Grzezczak, Mrinal K. Mandanl and Sethuraman Panchanathan, “VLSI Implementation of Discrete Wavelet Transform,” IEEE Trans. On VLSI Systems, vol. 4, no. 4, Dec 1996.
[25] C.Yu and S.J Chen, ”Efficient VLSI Architecture for Separable 2-D Dsicrete Wavelet Transforms,” IEEE International Symposium on Consumer Electronics, Oct 1998.
[26] Neil H.E. Weste, Kamran Eshraghian, ” RINCIPLE OF CMOS VLSI DESIGN A Systems Perspective,” second edition, ADDISON-WESLEY, Oct 1994.
[27] Gilbert Strang and Truong Nguyen, “ Wavelets and Filter Banks,” Wellesely-Cambridge, July 1996.
[28] Acharya. T, “A HIGH Speed Reconfigurable Integrated Architecture for DWT,” IEEE Global Telecommunications Conference, vol. 2, pp. 669-673, Nov 1997.
[29]M.Vishwanath and R.M. Owens, “A Common Architecture For the DWT and IDWT,” IEEE Conference on Application Specific Systems, Architectures and Processors, Aug 1996.
[30] Senung-Kwon Paek and Lee-Sup Kim, “2D DWT VLSI architecture for wavelet image processing,” IEEE Eltronics Letters, vol. 34, pp. 537-538, March 1998.
[31] Chio.H., Burleson W.P. and Phatak. D.S., “Optimal wordlength assignment for the discrete wavelet transform in VLSI,” IEEE VLSI Signal Processing, VI, pp. 325-333, Oct 1993.
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