數位視訊的處理在我們的生活應用方面已經有愈來愈重要的趨勢 .本篇論文主要是利用數位訊號處理器, 對視訊信號做處理,以達到即時編解碼的結果. 我們先對視訊傳輸處理的標準H.263做一說明, 隨後所做的訊號處理及以此規範為標準. Texas Instruments' TMS320C62xx 是一顆功能強大的訊號處理器,為近來TI 所全力推廣. 我們採用此處理器以透過其在訊號處理方面的特殊能力,來幫助實現即時視訊的編解碼目的.在編碼上,我們使用Telenor Research提供的免費Tmn 2.0 程式並加以修改, 改變其整體架構,使其整體處理速度加快.並且加入Tmn 3.1.1的改進部分,亦即運動向量預測使用鑽石型搜尋. 本論文討論TMS320C62xx的特性, 如何使用其特性以快速設計出高效率的程式,如何修改H.263編解碼程式以及修改後之結果.

The processing of digital video signal is having an increasing importance in our daily life. In this thesis, we use digital signal processor to deal with video signal and to achieve the goal of real-time. First, we give a brief introduction to the video communication standard H.263. All the reported work on video processing is based on this standard. Texas Instruments' TMS320C62xx is a powerful signal processor, and it is strongly marketed by TI. We choose this processor to avail ourselves of its special functionality in signal processing to help realize real-time video coding and decoding. We use Telenor Research's public domain software Tmn 2.0, and modify its architecture to speed up the processing. And we add in some improvement from the Tmn3.1.1, namely, diamond search in motion estimation. This thesis discusses the features of TMS320C62xx and modify a highly efficient program, how to modify the H.263 codec program, and the results of such modification.

Contents
Table of Contents III
List of Figures IV
List of Tables V
1 Introduction 1
2 Introduction to H.263 3
2.1 The Basic H.263 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 Intra?and Inter frame Coding . . . . . . . . . . . . . . . . . . 4
2.1.2 Different Motion-compensation and Quantization Modes . . . 8
2.1.3 Bitstream Synchronism . . . . . . . . . . . . . . . . . . . . . . 9
2.1.4 Choice of the Coding Mode . . . . . . . . . . . . . . . . . . . 9
2.1.5 Motion Vector Prediction . . . . . . . . . . . . . . . . . . . . 10
2.1.6 Coding Rate Control . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 H.263 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Compatibility Issue in Implementation . . . . . . . . . . . . . . . . . 11
3 Introduction to TI TMS320C62xx 13
3.1 The VLIW Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 The Core of C62xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 TI's Code Development Environment . . . . . . . . . . . . . . . . . . 26
3.5 The Code Composer . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Programming the C62xx 28
4.1 Optimization (Software Pipeline) . . . . . . . . . . . . . . . . . . . . 28
4.2 Techniques that Make Use of the Special Features of C62xx . . . . . . 33
4.2.1 Use Internal Memory . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.2 Use Intrinsics Whereever Possible . . . . . . . . . . . . . . . . 33
4.2.3 Short Format for Multiplication . . . . . . . . . . . . . . . . . 33
4.2.4 Use nassert Intrinsic and .trip . . . . . . . . . . . . . . . . . . 34
4.2.5 Use 32-bit Loads and Stores If Possible . . . . . . . . . . . . . 34
4.2.6 Try to Unroll Loops If They Are Short . . . . . . . . . . . . . 35
4.2.7 Separate Data Dependencies to Balance Resources . . . . . . . 35
4.2.8 Reduce Loading/Storing Times . . . . . . . . . . . . . . . . . 36
4.2.9 Memory Dependency . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.10 Data Memory and Program Memory . . . . . . . . . . . . . . 36
4.2.11 Run-time Library . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.12 Memory Model for Code Writing . . . . . . . . . . . . . . . . 37
4.3 How to Use and Write a DSP Program for C62xx . . . . . . . . . . . 37
4.3.1 Configure the Settings of Compiler Options . . . . . . . . . . 38
4.4 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.4.1 Special Functions of The ``Code Composer'' . . . . . . . . . . 41
4.4.2 How to Modify Heap into Two Parts in rts.src . . . . . . . . . 41
5 H.263 Codec Implementatiob on A C62xx 43
5.1 Encoder Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2 Fast Motion Estimation . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3 Fixed-point DCT/IDCT . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.4 Half-pixel Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.5 Total Cycles of Intra and Inter Frames . . . . . . . . . . . . . . . . . 51
5.6 Comparision Between The Original Program and The Optimized Pro?
gram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.6.1 Intra Frame in Internal Memory . . . . . . . . . . . . . . . . . 53
5.6.2 Inter Frame in Internal Memory . . . . . . . . . . . . . . . . . 54
5.6.3 Non-pipelined v.s Pipelined codes . . . . . . . . . . . . . . . . 54
5.6.4 Optimized Code in External and Internal Memories . . . . . . 55
5.6.5 Non-pipelined and Pipelined: Both in External Memory . . . 57
5.6.6 Subjective Results . . . . . . . . . . . . . . . . . . . . . . . . 59
6 Conclusions and Future Work 62

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