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研究生:吳國豪
研究生(外文):Kwo-Hau Wu
論文名稱:電漿處理後溫差液相沈積含氟矽氧化膜特性之研究及其在銅製程上之應用
論文名稱(外文):Investigation of Plasma Treated Temperature-Difference Liquid Phase Deposition FSG and Application on Damascene Process
指導教授:葉清發
指導教授(外文):Ching-Fa Yeh
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:英文
論文頁數:146
中文關鍵詞:溫差液相沈積含氟矽氧化膜液相沈積設備電漿處理阻障介電層
外文關鍵詞:Temperature-Difference Liquid Phase DepositionFSGLPD equipmentPlasma annealingbarrier dielectric
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在本研究中, 首先我們設計並組裝了一部嶄新的自動化液相沈積(LPD)設備。本裝置整體的管路可用PLC控制,避免了人員污染及安全問題。此外,由初步的測試結果發現,利用本裝置所成長的液相沈積氧化矽薄膜具有較佳的特性。
而為了進一步提高溫差液相沈積含氟矽氧化膜(TD-LPD FSG)之可靠性,我們對溫差液相沈積含氟矽氧化膜施以N2O及NH3 電漿處理並研究其抗濕性。結果發現,經N2O電漿處理後之溫差液相沈積含氟矽氧化膜介電常數值雖然略微上昇,但其抗濕性卻有效地被改善。然而, 溫差液相沈積含氟矽氧化膜經NH3電漿處理後則無此效果,僅介電常數值上昇而已。顯然,N2O 電漿處理後之溫差液相沈積含氟矽氧化膜非常適合單一地或與其他介電層結合作為導線間介電層(IMD)。而再根據二次離子質譜(SIMS)及熱脫附質譜儀(TDS) 之分析結果,我們亦提出了一項新的機制來解釋此電漿處理之效應。
接著,我們並首次提出以NH3電漿處理後之溫差液相沈積含氟矽氧化膜來作為銅之阻障介電層。因為具有絕佳之步階覆蓋性﹑且能有效地阻擋銅擴散,及特優的電性絕緣能力,若使用此阻障介電層來取代高電阻值之阻障金屬層(barrier metal)及襯墊氧化層(oxide liner),將可有效降低銅導線整體電阻及導線間漏電流,可大幅改善電阻-電容延遲(RC delay),因此在未來銅導線/低介電常數(low-K)介電質之嵌刻(damascene)製程中,極具應用潛力。
A novel automatic LPD (liquid phase deposition) bench is designed and assembled. The person-related contamination induced during operation and the security problems of the nowaday equipment is improved. The higher quality of LPD oxides prepared by this novel automatic LPD bench is verified.
To further improve the reliability of TD-LPD (temperature-difference liquid phase deposition) FSG, effects of N2O and NH3 plasma annealing on TD-LPD FSG in terms of moisture resistance have been investigated. N2O plasma annealing is effective in improving moisture resistance of the FSG at the expense of increased K value. However, NH3 plasma annealing increases the K value without improving the moisture resistance. Obviously, N2O plasma annealed TD-LPD FSG is promising as IMD, stand-alone or in combination with other dielectric. Accompanied with the investigation of the secondary ion mass spectroscopy (SIMS) and thermal desorption spectroscopy (TDS), a novel mechanism that accounts for plasma annealing effects is proposed.
In this work, a novel barrier dielectric prepared by temperature-difference based liquid phase deposition with NH3 plasma annealing is also proposed for the first time. In terms of (1) superior step coverage (95%) (2) effective prevention of Cu penetration and (3) gate oxide level quality, the barrier dielectric is very potential to replace both the barrier metal and the dielectric liner used in Cu/low-K dielectric damascene integration scheme for minimizing RC delay and leakage cu
Contents
Chinese Abstract Ⅰ
English Abstract Ⅱ
Acknowledgements Ⅲ
Contents Ⅳ
Table Captions Ⅶ
Figure Captions Ⅷ
Chapter 1 Introduction
1.1 Background 1
1.2 Motivation 2
1.3 Thesis Organization 3
Chapter 2 Development of Integrated Liquid Phase Deposition Equipment
2.1 Introduction 5
2.2 Experimental Procedures 6
2.3 Results and Discussions 7
2.3.1 Operation of Manual LPD Equipment and Its Disadvantages 7
2.3.2 Design of Integrated LPD Equipment 9
2.3.3 Test Results of The Integrated LPD Equipment 11
2.4 Summary 12
Chapter 3 Plasma Annealing Effects on TD-LPD FSG
3.1 Introduction 14
3.2 Experiment Procedures 15
3.2.1 Preparation of TD-LPD FSG 15
3.2.2 Plasma Annealing of TD-LPD FSG 15
3.2.3 Measurement 16
3.3 Results and Discussions 17
3.3.1 Thickness 17
3.3.2 Refractive Index 18
3.3.3 Dielectric Constant 19
3.3.4 Leakage Current 20
3.3.5 FTIR Spectra 21
3.3.6 SIMS Depth Profile 22
3.3.7 TDS Spectra 23
3.3.8 Plasma annealing Effects on TD-LPD FSG Prepared by Integrated LPD Equipment 24
3.4 Summary 25
Chapter 4 Novel Barrier Dielectric Prepared by Temperature-Difference based Liquid Phase Deposition with Plasma Annealing
4.1 Introduction 27
4.2 Experiment Procedures 28
4.2.1 Fabrication of MIS Test Structure 28
4.2.2 Measurement 29
4.3 Results and Discussions 30
4.3.1 Leakage Current 30
4.3.2 SIMS Depth Profile 31
4.3.3 Bias-Temperature Test 32
4.4 Summary 35
Chapter 5 Barrier Metal Free Damascene Structure with Cu and Low Dielectric
5.1 Introduction 37
5.2 Experiment Procedures 38
5.2.1 Fabrication of Test Structure for K-value Measurement 38
5.2.2 MIS Test Structure for J-E Measurement 39
5.2.3 Fabrication of Test Structure for Bias-Temperature Stress 40
5.2.4 IMD Trenches for Barrier Metal Free Damascene 41
5.2.5 Measurement 41
5.3 Results and Discussions 42
5.3.1 Effect on K value for MSQ capped by LPD Barrier Dielectric 42
5.3.2 Insulating Property of the LPD Barrier Dielectric 44
5.3.3 Barrier Performance of NH3 Plasma Annealed FSG/MSQ Stack Oxide 44
5.3.4 Fabrication of IMD Trenches with LPD Barrier Dielectric 47
5.4 Summary 49
Chapter 6 Conclusions
Conclusions 51
Reference 54
Publications i
Vita iii
Chapter 1
[1] M. S. Chen, J. S. Chou, and S. C. Lee, IEEE Electron Devices, 1995.
[2] C. F. Yeh et al., "Novel Technique for SiO2 Formed by Liquid-Phase Deposition for Low-Temperature Processed Polysilicon TFT", IEEE Electron Device Lett., EDL-14,403 (1993).
[3] C. F. Yeh et al ., "Performance and Off-State Current Mechanism of Low-Temperature Processed Polysilicon Thin-Film Transistors with LPD-SiO2 Gate Insulator", IEEE Electron Device, ED-41, No. 2, p. 173-179, (1994).
[4] C. F. Yeh et al., "Low-Temperature Processed Poly-Si TFT Using Solid Phase Crystallization and Liquid-Phase Deposition Gate Oxide", Jpn. J. Appl. Phys. Vol. 33, Part 1, No. 4, pp. 375-379, (1994).
[5] C. F. Yeh et al., "Thinner Liquid-Phase Deposited Oxide for Polysilicon Thin-Film Transistors", IEEE Electron Device Lett., Vol. 16, No. 11, p. 473, (1995).
[6] C. F. Yeh et al., "Thinner Liquid Phase Deposition (LPD) Oxide as Gate Insulator for Small-Geometry Poly-Si TFT''s", International Display Research Conference, monterey, USA, Oct.10-13, p. 303-306, (1994).
[7] C. F. Yeh et al., "Low-Temperature Processed MOSFET''s with Liquid Phase Deposition SiO2-xFx as Gate Insulator", IEEE Electron Device Lett., Vol. 16, No. 7, p. 316, (1995).
[8] C. F. Yeh et al., "Fabrication of MOSFET''s Using Low-Temperature Liquid-Phase Deposited Oxide", Microelectronic Enginneering 28, p. 101, (1995).
[9] C. F. Yeh, C. H. Liu, and J. L. Su, "Novel Contact Hole Fabrication Using Selective Liquid-Phase Deposition Instead of Reactive Ion Etching", IEEE Electron Device Latt., vol.20, No.1, January (1999)
[10] C. F. Yeh, Y. C. Lee, S. C. Lee, "N2O-Plasma Annealed TD-LPD FSG as SOG''s Cap layer", VIMC, p. 598-600, (1998)
[11] M. P. Houng, et al., " Near Room Temperature Growth of SiO2 Films for p-HgCdTe Passivation by Liquid Phase Deposition", Jpn. J. Appl. Phys. Vol. 36, pp.L696-L698, (1997)
[12]Su-Chen Lee, "Investigation of Temperature-Difference Liquid Phase Deposition SiO2-xFx Film", Master Thesis, Institute of Electronic, Nation Chiao Tung University, (1998)
[13] E.M. Zielinski, S.W. Russell, R.S. List, A.M. Wilson, C. Jin, K.J. Newton, J.P. Lu, T. Hurd, W.Y. Hsu, V. Cordasco, M. Gopikanth, V. Korthuis, W. Lee, G. Cerny, N.M. Russel, P.B. Smith, S. O''Brien, and R.H. Havemann, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), 936 (1997)
[14] H. Aoki, S. Yamasaki, T. Usami, Y. Tsuchiya, N. Ito, T. Onodera, Y. Hayashi, K. Ueno, H. Gomi, and N. Aoto, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), 777 (1997)
[15]S.C. Sun, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), 765 (1997).
[16]S.C. Sun, M.H. Tsai, H.T. Chiu, S.H. Chuang, and C.E. Tsai, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM),61 (1995)
[17] J.P. Lu, W.Y. Hsu, J.D. Luttmer, L.K. Magel, and H.L. Tsai, J. Electrochem. Soc., 145, L21 (1998).
[18] J.P. Lu, W.Y. Hsu, G.A. Dixit, J.D. Luttmer, R.H. Havemann, and L.K. Magel, , J. Electrochem. Soc., 143, L279 (1996).
[19]Y. Huang, T.R. Yew, W. Lur, and S.W. Sun, Proc. of 15th VLSI Multilevel Interconnection Conference (VMIC), 33 (1998)
[20] K. Mikagi, H. Ishikawa, T. Usami, M. Suzuki, K. Inoue, N. Oda, S. Chikaki, I. Sakai, and T. Kikkawa, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), 365 (1996)
[21] S. Takeishi et al., "Stabilizing Dielectric Constant of Fluorine-Doped SiO2 films by N2O-plasma Annealing", J. Electrochem. Soc., vol. 143, no. 1, (1996)
[22] Aniruddha B. Joshi et al.," High field Breakdown in Thin Oxides Grown in N2O Ambient", IEEE Trans on Electron Devices, vol. 40, no. 8, (1993)
[23] S. K. Lai et al., " Electrical Porperties of Nitrided-Oxide Systems for Use in Gate Dielectrics and EEPROM", IEDM Tech. Dig., p. 190, (1983)
[24] Takashi Hori, " Nitride Gate-Oxide CMOS Technology for Improved Hot-Carrier Reliability", Microelectronic Engineering 22, p. 245, (1993)
[25] G. W. Yoon et al. "MOS Characteristics of NH3-Nitrided N2O Grown Oxides", IEEE Electron Device Latt.,vol. 14, no. 4, p.179, (1993)
[26] M. Vogt et al., " PECVD of Oxynitride for Copper Metallization Systems", Microelectronic Engineering , 33, p. 349-356, (1997)
[27] Gopal Raghavan et al., "Diffusion of Copper through Dielectric Film under Bias Temperature Stress", Thin Solid Film , 262, p.168-176, (1995)
Chapter 2
[1] M. S. Chen, J. S. Chou, and S. C. Lee, IEEE Electron Devices, 1995.
[2] C. F. Yeh et al., "Novel Technique for SiO2 Formed by Liquid-Phase Deposition for Low-Temperature Processed Polysilicon TFT", IEEE Electron Device Lett., EDL-14,403 (1993).
[3] C. F. Yeh et al ., "Performance and Off-State Current Mechanism of Low-Temperature Processed Polysilicon Thin-Film Transistors with LPD-SiO2 Gate Insulator", IEEE Electron Device, ED-41, No. 2, p. 173-179, (1994).
[4] C. F. Yeh et al., "Low-Temperature Processed Poly-Si TFT Using Solid Phase Crystallization and Liquid-Phase Deposition Gate Oxide", Jpn. J. Appl. Phys. Vol. 33, Part 1, No. 4, pp. 375-379, (1994).
[5] C. F. Yeh et al., "Thinner Liquid-Phase Deposited Oxide for Polysilicon Thin-Film Transistors", IEEE Electron Device Lett., Vol. 16, No. 11, p. 473, (1995).
[6] C. F. Yeh et al., "Thinner Liquid Phase Deposition (LPD) Oxide as Gate Insulator for Small-Geometry Poly-Si TFT''s", International Display Research Conference, monterey, USA, Oct.10-13, p. 303-306, (1994).
[7] C. F. Yeh et al., "Low-Temperature Processed MOSFET''s with Liquid Phase Deposition SiO2-xFx as Gate Insulator", IEEE Electron Device Lett., Vol. 16, No. 7, p. 316, (1995).
[8] C. F. Yeh et al., "Fabrication of MOSFET''s Using Low-Temperature Liquid-Phase Deposited Oxide", Microelectronic Enginneering 28, p. 101, (1995).
[9] C. F. Yeh, C. H. Liu, and J. L. Su, "Novel Contact Hole Fabrication Using Selective Liquid-Phase Deposition Instead of Reactive Ion Etching", IEEE Electron Device Latt., vol.20, No.1, January (1999)
[10] C. F. Yeh, Y. C. Lee, S. C. Lee, "N2O-Plasma Annealed TD-LPD FSG as SOG''s Cap layer", VIMC, p. 598-600, (1998)
[11] M. P. Houng, et al., " Near Room Temperature Growth of SiO2 Films for p-HgCdTe Passivation by Liquid Phase Deposition", Jpn. J. Appl. Phys. Vol. 36, pp.L696-L698, (1997)
[12] C. F. Yeh et al. "The Physicochemical Properties and Growth Mechanism of Oxide (SiO2-xFx) by Liquid Phase Deposition with H2O Addition Only", J. Electrochem. Soc. Vol. 141, No. 11, November (1994)
[13]Su-Chen Lee, "Investigation of Temperature-Difference Liquid Phase Deposition SiO2-xFx Film", Master Thesis, Institute of Electronic, Nation Chiao Tung University, (1998)
Chapter 3
[1] Su-Chen Lee, "Investigation of Temperature-Difference Liquid Phase Deposition SiO2-xFx Film", Master Thesis, Institute of Electronic, Nation Chiao Tung University, (1998)
[2]C. F. Yeh, Y. C. Lee, S. C. Lee, Proc. of EDMS 1997, pp.119-121
[3] C. F. Yeh, S. C. Lee, Y. C. Lee, Proc. of EDMS 1997, pp.122-124
[4]S. Takeishi et al., "Stabilizing Dielectric Constant of Fluorine-Doped SiO2 films by N2O-plasma Annealing", J. Electrochem. Soc., vol. 143, no. 1, (1996)
[5]Aniruddha B. Joshi et al.," High field Breakdown in Thin Oxides Grown in N2O Ambient", IEEE Trans on Electron Devices, vol. 40, no. 8, (1993)
[6] S. K. Lai et al., " Electrical Porperties of Nitrided-Oxide Systems for Use in Gate Dielectrics and EEPROM", IEDM Tech. Dig., p. 190, (1983)
[7] Takashi Hori, " Nitride Gate-Oxide CMOS Technology for Improved Hot-Carrier Reliability", Microelectronic Engineering 22, p. 245, (1993)
[8] G. W. Yoon et al. "MOS Characteristics of NH3-Nitrided N2O Grown Oxides", IEEE Electron Device Latt.,vol. 14, no. 4, p.179, (1993)
[9] Y.J. Mei, T.C. Chang, S.J. Chang, F.M. Pan, M.S.K. Chen, A. Tuan, S. Chou, and C.Y. Chang, Thin Solid Films, (1997), 308-309, pp. .501~506
[10] S. Takeshi, H. Kudoh, R. Shinohara, A. Tsukune, Y. Satoh, H. Miyazawa, M. Yamada, J. Electrochem. Soc., (1996), 143, pp.381~385
Chapter 4
[1] Mark T. Bohr, " Interconnect Scaling - The Real Limiter to High Performance ULSI", Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), p. 241-244, (1995)
[2] E.M. Zielinski, S.W. Russell, R.S. List, A.M. Wilson, C. Jin, K.J. Newton, J.P. Lu, T. Hurd, W.Y. Hsu, V. Cordasco, M. Gopikanth, V. Korthuis, W. Lee, G. Cerny, N.M. Russel, P.B. Smith, S. O''Brien, and R.H. Havemann, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), 936 (1997)
[3]H. Aoki, S. Yamasaki, T. Usami, Y. Tsuchiya, N. Ito, T. Onodera, Y. Hayashi, K. Ueno, H. Gomi, and N. Aoto, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), 777 (1997)
[4]S.C. Sun, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), 765 (1997).
[5]S.C. Sun, M.H. Tsai, H.T. Chiu, S.H. Chuang, and C.E. Tsai, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM),61 (1995)
[6] J.P. Lu, W.Y. Hsu, J.D. Luttmer, L.K. Magel, and H.L. Tsai, J. Electrochem. Soc., 145, L21 (1998).
[7] J.P. Lu, W.Y. Hsu, G.A. Dixit, J.D. Luttmer, R.H. Havemann, and L.K. Magel, , J. Electrochem. Soc., 143, L279 (1996).
[8]Y. Huang, T.R. Yew, W. Lur, and S.W. Sun, Proc. of 15th VLSI Multilevel Interconnection Conference (VMIC), 33 (1998)
[9]K. Mikagi, H. Ishikawa, T. Usami, M. Suzuki, K. Inoue, N. Oda, S. Chikaki, I. Sakai, and T. Kikkawa, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), 365 (1996)
[10]M. Vogt et al., " PECVD of Oxynitride for Copper Metallization Systems", Microelectronic Engineering , 33, p. 349-356, (1997)
[11]Gopal Raghavan et al., "Diffusion of Copper through Dielectric Film under Bias Temperature Stress", Thin Solid Film , 262, p.168-176, (1995)
[12] Hiroshi Miyazaki et al., " Time-Dependent Dielectric Breakdown of Interlevel Dielectrics for Copper Metallization", Jpn. J. Appl. Phys. Vol.35, pp. 1685-1689, (1996)
[13] S. Simon Wong et al., "Electrical Reliability of Cu and Low-K Dielectric Integration", Mat. Res. Soc. Symp. Proc. Vol. 511, p. 317-327, (1998)
[14] Alvin L. S. Loke et al., "Copper Drift in Low-K Polymer Dielectrics for ULSI Metallization", 1998 Symposium on VLSI Technology Digest of Technical Papers, p. 26-27, (1998)
[15]Su-Chen Lee, "Investigation of Temperature-Difference Liquid Phase Deposition SiO2-xFx Film", Master Thesis, Institute of Electronic, Nation Chiao Tung University, (1998)
[16] A. Labiadh et al., " Study of The Thermal Stability at the Cu/SiOF Interface", Microelectronic Engineering 33, p. 369-375, (1997)
[17] H. Nagayama, H. Honda, and H. Kawahara, J. Electrochem. Soc., vol. 135, p.2013, (1988)
Chapter 5
[1]E.M. Zielinski, S.W. Russell, R.S. List, A.M. Wilson, C. Jin, K.J. Newton, J.P. Lu, T. Hurd, W.Y. Hsu, V. Cordasco, M. Gopikanth, V. Korthuis, W. Lee, G. Cerny, N.M. Russel, P.B. Smith, S. O''Brien, and R.H. Havemann, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), 936 (1997)
[2]H. Aoki, S. Yamasaki, T. Usami, Y. Tsuchiya, N. Ito, T. Onodera, Y. Hayashi, K. Ueno, H. Gomi, and N. Aoto, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), 777 (1997)
[3]S.C. Sun, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), 765 (1997).
[4]S.C. Sun, M.H. Tsai, H.T. Chiu, S.H. Chuang, and C.E. Tsai, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM),61 (1995)
[5] J.P. Lu, W.Y. Hsu, J.D. Luttmer, L.K. Magel, and H.L. Tsai, J. Electrochem. Soc., 145, L21 (1998).
[6] J.P. Lu, W.Y. Hsu, G.A. Dixit, J.D. Luttmer, R.H. Havemann, and L.K. Magel, , J. Electrochem. Soc., 143, L279 (1996).
[7]Y. Huang, T.R. Yew, W. Lur, and S.W. Sun, Proc. of 15th VLSI Multilevel Interconnection Conference (VMIC), 33 (1998)
[8]K. Mikagi, H. Ishikawa, T. Usami, M. Suzuki, K. Inoue, N. Oda, S. Chikaki, I. Sakai, and T. Kikkawa, in Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM), p. 365 (1996)
[9]M. Vogt et al., " PECVD of Oxynitride for Copper Metallization Systems", Microelectronic Engineering , 33, p. 349-356, (1997)
[10]Gopal Raghavan et al., "Diffusion of Copper through Dielectric Film under Bias Temperature Stress", Thin Solid Film , 262, p.168-176, (1995)
[11] Hiroshi Miyazaki et al., " Time-Dependent Dielectric Breakdown of Interlevel Dielectrics for Copper Metallization", Jpn. J. Appl. Phys. Vol.35, pp. 1685-1689, (1996)
[12] S. Simon Wong et al., "Electrical Reliability of Cu and Low-K Dielectric Integration", Mat. Res. Soc. Symp. Proc. Vol. 511, p. 317-327, (1998)
[13] Alvin L. S. Loke et al., "Copper Drift in Low-K Polymer Dielectrics for ULSI Metallization", 1998 Symposium on VLSI Technology Digest of Technical Papers, p. 26-27, (1998)
[14] C. F. Yeh, Darren C. Chen, C. Y. Lu, C. Liu, S. T. Lee, C. H. Liu and T. J. Chen, " Highly Reliable Liquid-Phase Deposited SiO2 with Nitrous Oxide Plasma Post-Treatment for Low Temperature Processed Poly-Si TFT''s ", Tech. Dig. IEEE Int. Electron Devices Meeting.(IEDM) (1998)
[15] C. F. Yeh, C. L. Chen, " Room-temperature selective Growth of Dielectric Films by Liquid-Phase Deposition", Semicond. Sci. Technol. 9, p. 1250-1254, (1994)
[16]C. F. Yeh, Y. C. Lee, S. C. Lee, "N2O-Plasma Annealed TD-LPD FSG as SOG''s Cap layer", VIMC, p. 598-600, (1998)
[17]Su-Chen Lee, "Investigation of Temperature-Difference Liquid Phase Deposition SiO2-xFx Film", Master Thesis, Institute of Electronic, Nation Chiao Tung University, (1998)
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