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研究生:蘇育清
研究生(外文):Yuh-Ching Su
論文名稱:極大型積體電路銅製程關鍵技術之研究-銅/溫差液相沈積含氟矽氧化膜/低介電常數MSQ之製程整合
論文名稱(外文):Investigation of ULSI Damascene Key Process-Process Integration of Cu/Temperature Difference Liquid Phase Deposition SiOF/Low K MSQ
指導教授:葉清發
指導教授(外文):Ching-Fa Yeh
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:英文
中文關鍵詞:溫差液相沈積含氟矽氧化膜低介電常數氧電漿損害側壁覆蓋
外文關鍵詞:Cutemperature-difference liquid phase depositionSiOFlow KO2 plasma damageMSQsidewall capping
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為了降低RC delay, 銅和低介電絕緣材料之製程整合是未來後段製程的重大議題。由於銅在乾蝕刻時生成物不易揮發,傳統的鋁製程已被嵌刻 (Damascene) 製程取代。然而低介電材料蝕刻完之後,在去光阻時會遭受氧電漿損害,因而造成介電值上升以及金屬導線氧化。
在本論文中,我們提出以溫差液相沈積二氧化矽含氟膜當低介電材料MSQ的壁覆蓋層以取代硬光罩製程來解決氧電漿損害問題。此含氟膜具有選擇性成長的特性,它不會沈積在光阻上,因此在去光阻前我們沈積此含氟膜在MSQ側壁上,然後去除光阻。此方法比硬光罩法製程簡單且與雙重嵌刻法相容。由於此膜是在室溫成長所以有極低應力值,並且它有良好的絕緣特性,可降低金屬間的漏電。這種製程技術同時改進了硬光罩以及二氧化矽襯墊層的問題。
此含氟膜在25℃成長時具有最低的介電質(~3.4),最低的硬力值(~41Mpa) 。因此適合用在後段製程。而且只要大約12.7nm的厚度就可抵抗氧電漿損害了。此外,為了提高此膜的抗濕性,我們使用笑氣電漿來作退火處理。
在嵌刻製程中,介電材料的蝕刻是很重要的,我們研究發現MSQ的蝕刻條件可只藉著只調CF4流量和射頻功率來獲得最佳的蝕刻條件。最後,為了去掉MSQ側壁聚合物,我們發展一種兩階段的處理方式,且此法並且不會對MSQ造成損害。總而言之,我們已發展出一種新的無氧電漿損害的嵌刻製程。

To reduce RC delay, integration of Cu and low K dielectric is an important issue in future back end of line (BEOL) process. Owing to the etching by-products of Cu are hard to volatile, conventional Al metallization was replaced by Damascene process. However, after low K dielectric patterning, the dielectric will suffer O2 plasma damage during stripping, and result in K value increment and metal line corrosion.
In thesis, to replace hard mask process, we propose a method of using TD-LPD FSG a MSQ's sidewall capping layer to avoid O2 plasma damage. This FSG has selective deposition characteristics i.e., it won't deposit on photoresist. Therefore, prior to photoresist stripping, we deposit this FSG on MSQ's sidewalls, then remove the photoresist. This method is more simple than hard mask process and compatible with dual Damascene process. This FSG exhibits low stress property owing to room deposition temperature. Besides, it has good isolating ability, which reduces leakage current between metal lines. The proposed method improves hard mask process and oxide linar process at one time.
the film deposited at 25℃ with lowest K value (~3.4), lowest stress value ( ~41Mpa). Therefore, it is suitable to be used in BEOL process. Furthermore, The FSG with thickness ~12.7nm is adequate to withstand O2 plasma damage. Besides, we use N2O plasma annealing to enhance the moisture absorption resistance of the FSG.
The dielectric etching process is very important in Damascene process. We found that
The optimal MSQ etching recipe can be obtained by adjust CF4 flow rate and RF power value only. Finally, to remove MSQ sidewall polymer, we developed a technique with two-step treatment, and which won't damage MSQ. To sum up, we have developed a novel O2 plasma damage free Damascene process.

Contents
Chapter 1 Introduction
1.1 Background 1
1.2 Motivation 3
1.3 Thesis Organization 4
Chapter 2 Investigation on Temperature-Difference Liquid-Phase Deposition Fluorosilicate Glass
2.1 Introduction 6
2.2 Experimental Procedures 7
2.3 Results and Discussions 8
2.4 Summary 13
Chapter 3 Immunity of Td-LPD FSG to O2 Plasma Damage
3.1 Introduction 14
3.2 Experiment Procedures 14
3.2.1 Low K SOD Film Formation 14
3.2.2 Preparation of TD-LPD FSG/Low K SOD Stack 15
3.2.3 Process and Measurement Apparatuses 16
3.3 Results and Discussion 16
3.4 Summary 17
Chapter 4 Investigation of the MSQ Etching Mechanism
4.1 Introduction 18
4.2 Experimental Procedures 20
4.2.1 Process Flow 20
4.2.2 Process and Measurement Apparatuses 20
4.3 Results and Discussion 21
4.3.1 Film Structure Difference between PECVD Oxide and MSQ 21
4.3.2 Effects of Oxygen on MSQ Etching 21
4.3.3 Effects of RF Power on MSQ Etching 22
4.3.4 Effects of CF4 on MSQ Etching 23
4.4 Summary 25
Chapter 5 Damage Free Damascene Process Using TD-LPD FSG as MSQ's Sidewell Capping Layer
5.1 Introduction 26
5.2 Experimental Procedures 28
5.2.1 Development of Polymer Removal Techniques 28
5.2.1.1 Ar Sputtering Technique 28
5.2.1.2 LPOP Ashing Technique 28
5.2.2 Incubation Time Measurement of TD-LPD FSG on MSQ Sidewalls 28
5.2.3 Process Flow of Damage Free Damascene Process 29
5.2.4 Formation of Cu/Ti/N2O Annealed LPD FSG/MSQ Stack 29
5.2.5 Process and Measurement Apparatuses 30 5.3 Results and Discussion 30
5.3.1 Polymer Removal Techniques and Reliability 31
5.3.2 Incubation Time Measurement of TD-LPD FSG Deposited on MSQ 32
5.3.3 Damage Free Damascene Process 32
5.3.3.1 Drawbacks of Conventional Hard Mask Damascene 32
5.3.3.2 Benefits of Proposed Novel Damascene Structure 32
5.3.3.3 Damage Free Damascene Structure Profiles 33
5.3.4 TDS Measurement of Patterned MSQ With/Without TD-LPD FSG Capping 34
5.3.5 Improve Moisture Absorption Resistance of
TD-LPD FSG Using N2O Plasma Annealing 34
5.4 Summary 36
Chapter 6 Conclusions 37

Chapter 1
[1] C.A. Mead, "Scaling of MOS Technology to submicron feature sizes", J. VLSI Signal Processing, Vol.8, pp.9-25, 1994
[2] Davari, B. "CMOS technology scaling, 0.1 /spl mu/m and beyond", 1996 IEDM p.555-558
[3] M,T, Bohr, "Interconnect Scaling - The Real Limiter to High Performance ULSI", IEDM 1995, pp241-244.
[4] Kyoji Yamashita, et al., "Impact of Crosstalk on Delay Time and a Hierarchy of Interconnects", 1998 IEDM, pp291-294
[5] Pei-Lin Pai, et al., "COPPER AS THE FUTURE INTERCONNECTION MATERIAL", 1989 VMIC, pp258-264
[6] Jiang Tao, et al., "Electromigration Characteristics of Copper Interconnects', IEEE Electron Device Letters, VOL. 14, NO. 5, MAY 1993
[7] C. K. Hu, et al., "Diffusion barrier studies for Cu', 1986 VMIC, P181
[8] Awaya, N. et al., "Evaluation of a Copper Metallization Process and the Electrical Characteristics of Copper-Interconneced Quarter-Micron CMOS", IEEE Transations on Electron Devices, VOL. 43, NO.8, August 1996
[9] Changsup Ryu, et al., "Electromigration of submicron Damascene copper interconnects", VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on , Page(s):156 -157
[10] M. Market, "Mechanism Studies of Cu RIE for VLSI interconnects", MAM'97, p155
[11] Kaanta, C.W. et al., "Dual Damascene: a ULSI wiring technology", 1991 VMIV, pp144-152
[12] Ikeda, M. et al., "Integration of organic low-k material with Cu-damascene employing novel process", Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International , Page(s): 131 -133
[13] Zhao, B. et al., "A Cu/low-/spl kappa/ dual damascene interconnect for high performance and low cost integrated circuits", VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on , Page(s):28 -29
[14] Aoki, H. et al., "A degradation-free Cu/HSQ damascene technology using metal mask patterning and post-CMP cleaning by electrolytic ionized water", 1996 IEDM, PP777-780
[15] Hayashi, Y. et al., "A new two-step metal-CMP technique for a high performance Multilevel interconnects featured by Al- and "Cu in low /spl epsiv/, organic film"-metallizations", VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on , Page(s): 88 -89
[16] Z. stavreva, et al., "Chemical-Mechanical polishing of copper for interconnect formation", Microelectronic Engineering 33 (1997), p249-257
[17] S. Nitta, et al., " Fabrication and characterization of spin-on silicaxerogel films",1998 MRS, pp99-104
[18] T. Ramos, et al., "Nanoporous silica for low K dielectrics', 1998 MRS, p105-110
[19] Abbe T. Kohl, et al., "Low K, Porous Methyl Silesquioxane and pin-On-Glass", Electrochemical and Solid-state Letters, 2 (2) 77-79 (1999)
[20] G. Passemard, "Single Damascene Intergation of BCB with Copper', 1998 VMIC, pp63-68
[21] Tue Nguyen, et al., "Integration of MOCVD Copper and Low-K Fluoronated Amorphous Carbon in Single Damascene Structures", 1998 VMIC, pp31-32
[22] Shin-Puu Jeng, et al., "Implementation of low-dielectric-constant materials for ULSI circuit performance improvement", 1995 international Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical papers, p164
[23] S. C. Sun, et al., " Thermal Stability and Stress Variation in Low Dielectric Constant Spin-On-Glass", 1996 VMIC, p113
[24] C. C. Chao, et al., "Low dielectric-constant-insulators for electronics applications", Materials chemistry and Physics 42, p91, 1995
[25] Y. Matsubara. Et al., "Copper Damascene using low dielectric constant fluorinated amorphous carbon interlayer", 1998 MRS, pp291-296
[26] M. matsuura, et al., "A highly Reliable Self-Plannarizing Low-K Intermetal Dielectric for Sub-quarter Micron Interconnects" 1997 IEDM, p.785-788
[27] M. Hamanaka, et al., "Via Failures Due to Water Emission from SOG", 1994 IEEE/IRPS, p405~409
[28] J. D. Romero, et al., "Outgassing behavior of spin-on-glass (SOG)", 991 MRS, p1996~2003
[29] E. M. Zielinski, et al., "Damascene Integration of Copper and Ultra-Low-k Xerogel for High Performance Interconnects", 1997 IEDM, pp936-938
[30] Isobe, A., et al., "Dielectric film influence on stress-migration", VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE , Page(s): 363 -364
[31] A. S. Oates, IEEE Proceedings 31st IPRS, P297 (1993)
[32] L .A. Miller, et al., Proc. Of 12th VMIC, p369, 1995
[33] Baldini, "Interaction between electromigration and mechanical-stress-induced migration; New insights by a simple, wafer-level resistometric technique", Electron Devices, IEEE Transactions on Volume: 38 3 , Page(s): 469 -475
[34] Hoshino, K., et al., "Electromigration after stress-induced migration test in quarter-micron Al interconnects", Reliability Physics Symposium, 1994. 32nd Annual Proceedings, IEEE International, Page(s): 252 -255
[35] C. F. Yeh, et al., "Newly developed low-K and low stress fluorinated silicon oxide utilizing temperature-difference liquid-phase deposition technology", Materials Research Society 1998 Spring meeting
[36] C. F. Yeh, et al., "Effects of thermal annealing and moisture stress on low-K LPD SiO2-xFx deposited without addition of water", 1997 Electronic Device and Materials Symposium, p122, 1997
[37] C. F. Yeh, et al., "Applying selective liquid-phase deposition to create contact holes in plasma damage-free process", Plasma Process-Induced Damage, 1998 3rd International Symposium on , Page(s):223 -226
[38] C. F. Yeh, et al., "Novel contact hole fabrication using selective liquid-phase
deposition instead of reactive ion etching", IEEE Electron Device Letters
Volume: 20 1, Page(s): 39 -4
[39] C. F. Yeh, et al., "N2O-plasma annealed TD-LPD FSG as SOG's Cap Layer", 1998 VLSI Multilevel Interconnection Conference
[40] Y. J. Mei, et al., "Stabilizing dielectric constant of fluorine-doped SiO2 film by N2O and NH3 plasma post-treatment", Thin Solid Films, p501, 1997
Chapter 2
[1] M.T. Bohr, in Tech. Dig. IEEE Int. Electron Devices Meet., 241 (1995).
[2] C.F. Yeh, S.S. Lin, and W. Lur, Proc. of 13th VLSI Multilevel
Interconnection Conference (VMIC), 101 (1996).
[3] P.W. Lee, S. Mizuno, A. Verma, and H. Tran, and B. Nguyen, J.
Electrochem. Soc., 143, 2015 (1996).
[4] T. Homma, Thin Solid Films 278, 28 (1996).
[5] M. Yoshimaru, S. Koizumi, K. Shimokawa, and J. Ida, in Proceedings of the 35th Annual IEEE International Reliability Physics Symposium, 234 (1997).
[6] H. Miyajima, R. Katsumata, Y. Nakasaki, Y. Nishiyama, and N. Hayasaka, Jpn. J. Appl. Phys., 35, 6217 (1996).
[7] M.K. Jain, K.J. Taylor, G.A. Dixit, W.W. Lee, L.M. Ting, G.B. Shinn, S. Nag, R.H. Havemann, J.D. Luttmer, and M. Chang, Proc. of 13th VLSI Multilevel Interconnection Conference (VMIC), 23 (1996).
[8] I. Goswami and M.J. Loboda, Proc. of 14th VLSI Multilevel Interconnection Conference (VMIC), 632 (1997).
[9] C.F. Yeh, Y.C. Lee, and S.C. Lee, Proc. of 15th VLSI Multilevel Interconnection Conference (VMIC), 598 (1998).
[10] M.L. Dreyer and P.S. Ho, in HANDBOOK OF MULTILEVEL METALLIZATION FOR INTEGRATED CIRCUITS: Materials, Technology, and Applications, S.R. Wilson and C.J. Tracy, Editors, Ch.8 (1993).
[11] L.A. Miller and A.K. Stamper, in Proc. of 12th VLSI Multilevel Interconnection Conference (VMIC), 369 (1995).
[12] C.F. Yeh, Y.C. Lee and S.C. Lee, Mat. Res. Soc. Symp. Proc., 511, 57 (1998)
[13] C.F. Yeh, S.S. Lin, and Water Lur, J. Electrochem. Soc. 143, 2658 (1996)
[14] Y. Sakai, T. Goda, A. Hishinuma, and H. Kawahara, Proceeding of the International Ceramics Conference (AUSTCERAM 90), P.474 (1990)
[15] H. Kawahara, Y. Sakai, T. Goda, A. Hishinuma and K. Takamura, SPIE Vol. 1513 Glasses for Optoelectronics II, p.198 (1991)
[16] W.A. Pliskin, J. Vac. Sci. Technol. 14, 1064 (1977)
[17] C.F. Yeh, C.L. Chen, and G.H. Lin, J. Electrochem. Soc. 141, 3177 (1994)
[18] W.A. Pliskin and H.S. Lehman, J. Electrochem. Soc. 112, 1013 (1965)
[19] S.W. Lim, Y.Shimogaki, Y. Nakano, K. Tada, and H. Komiyama, J. Electrochem. Soc. 144, 2531 (1997)
[20] J.H. Wei, and S.C. Lee, J. Electrochem. Soc. 144, 1870 (1997)
[21] S. Wolf and R.N. Tauber, SILICON PROCESSING FOR THE VLSI
ERA, Vol. 1, p.115 (1986)
[22] M. Nakamura, R. Kanzawa, and K. Sakai, J. Electrochem. Soc. 133,
1167 (1986)
[23] T.H. Fan, S.S. Lin and C.F. Yeh, Extended Abstract of the 1995 International Solid State Devices and Materials (SSDM'95), 596
(1995)
Chapter 3
[1] Isobe, A., et al., "Dielectric film influence on stress-migration", VLSI Multilevel
Interconnection Conference, 1990. Proceedings, Seventh International IEEE ,
Page(s): 363 -364
[2] A. S. Oates, IEEE Proceedings 31st IPRS, P297 (1993)
[3] L .A. Miller, et al., Proc. Of 12th VMIC, p369, 1995
[4] Aoki, H. et al., "A degradation-free Cu/HSQ damascene technology using metal
mask patterning and post-CMP cleaning by electrolytic ionized water", 1996
IEDM, PP777-780
[5] S. C. Lee, "Investigation of Temperature-difference Liqui-Phase Deposited SiO2-
xFx Film", NCTU master thesis, p103, 1998
[6] M. Hamanaka, et al., "Via Failures Due to Water Emission from SOG", 1994
IEEE/IRPS, p405~409
[7] J. D. Romero, et al., "Outgassing behavior of spin-on-glass (SOG)", 991 MRS, p1996~2003
[8] Berti, A.C., et al., "Manufacturing advancements in an organic SOG process by Ar/sup +/ implantation", Advanced Semiconductor Manufacturing Conference and Workshop, 1996. ASMC 96 Proceedings. IEEE/SEMI 1996 , Page(s): 259 -264
Chapter 4
[1] M. R. Baklanov, et al., "Plasma etching of organic low-dielectric-constant polymers: comparative analysis", 1998 MRS, p247-252
[2] J. W. Cobirn, et al., J. Vac. Sci. Technol., 16, 39 (1979)
[3] C. J. Mogab, et al., J. Appl. Phys., 49, 3796 (1978)
[4] Flora. S. Ip, et al., "Integration of low dielectric constant materials with 0.25μm ALUMINUM Interconnects", 1996 MR, p59
[5] S. R. Cain, et al., J. Vac. Sci. Technol., A5(4), p1578 (1987)
[6] Stanley Wolf, "Silicon Processing For the VLSI era", VOL. 1, p549
Chapter 5
[1] G. S. Oehrlein, et al., J. Vac. Sci. Technol., A12, 323 (1994)
[2] G. S. Oehrlein, et al., J. Vac. Sci. Technol., A12, 333 (1994)
[3] J. W. Coburn, J. Appl. Phys., 50, 5210 (1979)
[4] Ying Wang, et al., "Understanding of Via-Etch-Induced Polymer Formation and Its Removal", J. Electrochem. Soc., Vol. 144, No.4, p1522, April 1997
[5] S. kato, et al., ibid., A12, 1204 (1994)
[6] P. Simko, et al., J. Electrochem. Soc., 138, 277 (1992)
[7] W. M. Lee, et al., The Electrochemical Society Proceeings Series, PV 93-25, P326 ,Pennington, NJ (1993)
[8] S. J. Kirk, et al., Technical Proceedings, Singapore (1995)
[9] S. C. Lee, "Investigation of temperature-Difference Liquid-Phase Deposited SiO2-xFx Film", 1998 NCTU master thesis
[10] C. F. Yeh, et al., "N2O-plasma annealed TD-LPD FSG as SOG's Cap Layer", 1998 VLSI Multilevel Interconnection Conference
[11] Y. J. Mei, et al., "Stabilizing dielectric constant of fluorine-doped SiO2 film by N2O and NH3 plasma post-treatment", Thin Solid Films, p501, 1997
[12] M. Matsuura, et al., "A highly Reliable Self-plannarizing Low-K Intermetal Dielectric for sub-quarter Micron Interconnects", 1997 IEDM, p785-788

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