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研究生:游正達
研究生(外文):Gen-Da You
論文名稱:矽化鎳之製備及NiSi/p+n接面二極體的之研究
論文名稱(外文):Formation of NiSi and NiSi Silicided Junction Diodes
指導教授:陳茂傑
指導教授(外文):Mao-Chieh Chen
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:英文
論文頁數:92
中文關鍵詞:矽化鎳
外文關鍵詞:NiSinickel silicidenickel polycide
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本論文主要探討矽化鎳(NiSi)的材料特性與應用於超大型積體電路的相關的製程技術。特性優異的矽化鎳可在400到600 oC之製程溫度範圍內形成在單晶矽基底上。對於在接面深度為0.3微米的p+n接面上形成NiSi而言,最佳的製程是將鍍有鎳金屬的Ni/p+n在爐管中進行500 oC的熱處理30分鐘,如此所得之NiSi/p+n接面二極體的反向偏壓漏電流密度為12.7 nA/cm2。結構為 Ni/(doped)poly-Si/SiO2/Si的試片在爐管中作500 oC 的熱處理30分鐘或在快速退火爐中作450 oC熱處理1分鐘,都可得到電性極佳的NiSi-polycide MOS結構。本論文也探討以離子植入矽化鎳的技術來製作NiSi/p+n淺接面二極體。在BF2+離子以60 KeV能量及1×1015 cm-2劑量植入NiSi/n-Si,並在爐管中作700 oC 的退火處理30分鐘所得之NiSi/p+n接面二極體,其接面深度不及0.15微米,且其反向偏壓漏電流密度僅為20 nA/cm2。

This thesis studies the material properties and process technologies of nickel silicide relevant to VLSI applications. The process window for the formation of good quality NiSi films on single crystalline silicon substrate ranges from 400 to 600 oC. The optimal process for the formation of silicide contacted NiSi/p+n junction diodes with a junction depth of 0.3  m, is a 30 min furnace annealing at 500 oC, and the leakage current density of the resultant diodes was found to be 12.7 nA/cm2. For the samples of Ni/(doped) poly-Si/SiO2/Si structure, thermal annealing in furnace for 30 min at 500 oC or RTA annealing for 1 min at 450 oC resulted in a NiSi-polycide MOS capacitor of optimum I-V characteristics and charge-to-breakdown. For the NiSi/p+n shallow junction diodes fabricated using implant through silicide scheme, BF2+ implantation at 60 KeV to a dose of 1x1015 cm-2 followed by a 30 min 700 oC furnace anneal resulted in NiSi/p+n shallow junction diodes having a junction depth less than 0.15 m and with the reverse bias leakage current density as low as 20 nA/cm2.

Chapter 1 Introduction 1
1.1 Self-aligned-silicide Process 1
1.2 Problems with TiSi2 and CoSi2 2
1.3 Advantages of NiSi Process 3
1.4 Thesis 4
Chapter 2 NiSi Formation and NiSi Silicided p+n
Junction Diodes 6
2.1 Nickel Silicide (NiSi) Formation 6
2.2 NiSi/p+n Junction Diodes Fabrication 6
2.3 Results and Discussion 7
2.3.1 I-V Characteristics 7
2.3.2 Sheet Resistance 8
2.3.3 XRD 9
2.3.4 SEM 10
2.3.5 AES 11
2.3.6 SIMS 11
2.4 Summary 12
Chapter 3 NiSi-polycide and Thin Gate Oxide Using
NiSi-polycide Structure 13
3.1 Introduction 13
3.2 NiSi Polycide 14
3.2.1 Experimental Procedure 14
3.2.2 Sheet Resistance 14
3.2.3 XRD 15
3.2.4 SEM 15
3.3 NiSi-polycide Gate MOS Capacitor 16
3.3.1 Experimental Procedure 16
3.3.2 I-V Characteristics 17
3.3.3 Time Dependent Dielectric Breakdown (TDDB) 19
3.4 Summary 20
Chapter 4 Formation of p+n Shallow Junction Using Implant
into/through Nickel Silicide Technology 21
4.1 Introduction 21
4.2 Experimental Procedure 22
4.3 Results and Discussion 23
4.3.1 Ion Implantation Simulation 23
4.3.2 Electrical Characteristics 23
4.3.3 SIMS 24
4.4 Summary 25
Chapter 5 Conclusions 26
Reference 28

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[2] J. R. Pfiester, T. C. Mele, Y. Limb, R. E. Jones, M. Woo, B. Boeck and C. D.Gunderson, “A TiN strapped polysilicon gate cobalt salicide CMOS process,in IEDM Tech. Dig., pp. 241-244, 1990.
[3] R. Liu, D. S. Williams, and W. T. Lynch, “Mechanism for process induced leakage current in shallow silicided junctions,” in IEDM Tech. Dig., pp. 58-61, 1986.
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[7] H. Jeon, C. A. Sukow, J. W. Honeycutt, G. A. Rozgonyi, and R. J. Nemanich, “Morphology and phase stability of TiSi2 on Si,” J. Appl. Phys., vol. 71. No. 9, p. 1, 1992.
[8] M.-A. Nicolet and S. S. Lau, “Formation and characterization of transition-metal silicides,” in VLSI Electrons : Microstructure Science vol. 6, Chapter 6,Academic Press, pp. 457, 346, 358, 1983.
[9] Tatsuya Ohguro, Shin-ichi Nakamura, Mitsuo Koike, Toyota Morimoto, Akira Nishiyama, Yukihiro Ushiku, Takashi Yoshitomi, Muzuki Ono, Masanobu Saito, Hiroshi Iwai,“Self-aligned nickel-mono-silicide technology for high speed deep submicrometer logic CMOS ULSI,"IEEE Trans. Electron Devices, vol. 42, p. 915,1995.
[10] V. Probst, H. Schaber, A. Mitwalsky, H. Kabza, and B. Hoffmann, “Metal-dopant-compound formation in TiSi2 and TaSi2 : Impact on dopant diffusion and contact resistance,” J. Appl. Phys., vol. 70, no. 2, p. 693, 1991.
[11] N. I. Lee, Y. W. Kim and S. T. Ahn, “Effect of the Silicidation Reaction Condition on the Gate Oxide Integrity in Ti-polycide Gate,” Jpn. J. Appl. Phs.,Vol. 33, no. 1B, p. 672, 1994.
[12] Q. Wang, C. M. Osburn, C. A. Canovai, “Ultra-shallow junction formation using silicide as diffusion source and low thermal budget,"IEEE Trans. Electron Devices, vol. 39,p. 2486, 1992.
[13] D. L. Kwong, T. H. Ku, S. K. Lee, E. Louis, N. S. Alvi, and P. Chu, “Silicided shallow junction formation by ion implantation of impurity ions into silicide layers and subsequent drive-in,” J. Appl. Phys., vol. 61, p. 5084, 1987.
[14] B. Y. Tsui, M. C. Chen, “Formation and characterization of a PtSi contact n+p shallow junctions,” J. Appl. Phys., vol. 68, p. 2265, 1990.
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[16] R. G. Wilson, “Boron, fluorine, and carrier profiles for B and BF2 implants into crystalline and amorphous Si,” J. Appl. Phys., vol. 54, p. 6879, 1983.

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