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[1] Willian D. Brown, "Nonvolatile Semiconductor Memory Technology", p27 [2] Betty Prince, "Semiconductor Memories," second edition, p.182 [3] Willian D. Brown, "Nonvolatile Semiconductor Memory Technology", p126 [4] J. C. Lee, C. Hu, "Polarity asymmetry of oxide grown polycrystalline silicon", IEEE Transaction on Electron Devices. Vol.35, p.1063, 1988 [5] L. Faraone, "Thermal SiO2 films on the n+-polycrystalline silicon : electrical conduction and breakdown," IEEE Transaction on Electron Devices. Vol.33. p1785, 1986 [6] P. A. Heimann, S. P. Murarka, T.T.Sheng, "Electrical conduction and breakdown in oxides of polycrystalline silicon and their collection with interface texture," J. Appl. Phys. , vol.53, p.6240,1982 [7] J. Ahn, W. Ting, "High-quality MOSFET's with ultrathin LPCVD gate SiO2," IEEE Electron Device Lett., vol.13, p.186,1992 [8] M. Lenzlinger, E. H. Snow: J. Appl. Phys., vol.40, p.278-283,1982 [9] Z. H. Liu, P. T. Lai : "Characterization of Charge Trapping and High-Field Endurance for 15nm Thermally Nitrided Oxides", IEEE Transaction on Electron Devices., Vol.38, p.344, 1991 [10] C. Cobianu, O. Popa, "On the electrical conduction in the dielectric layer," IEEE Electron Device Lett., vol.14, p.213, 1993 [11] F. S. Becher, D. Pawlik, " Low pressure deposition of doped SiO2 by pyrolysis of tetraethylorthosilicate (TEOS) " J. Vac. Sci. Technol. B, vol.5 p.1555,1987 [12] C. H. Kao, C. S. Lai " The TEOS CVD Oxide Deposited on Phosphorus In Situ Doped Polysilicon with Rapid Thermal Annealing in N2O," IEEE Transaction on Electron [13] J. H. Klootwijk, M. H. H. Weusthof , " Improvements of deposited interpolysilicon dielectric characteristics with RTP N2O-anneal", IEEE Electron Device Lett., vol. 17, p.358, 1996 [14] H. Hwang, W. Ting, " Electrical and reliability characteristics of the ultra thin oxynitride prepared by rapid thermal processing in N2O," in IEDM Tech. Dig., p.421,1990 [15] F. S. Becker, D. Pawlik, "Low-pressure deposition of high-quality SiO2 films by pyrolysis of tetraethylorthosilicate" J. Vac. Sci. Technol., vol. B5, p1555, 1987 [16] C. H. Kao, C. S. Lai " The TEOS CVD Oxide Deposited on Phosphorus In Situ Doped Polysilicon with Rapid Thermal Annealing," IEEE Electron Device Lett., vol.44, p.526, 1997 [17] J. Lee, C. Hu, "Comparison between CVD and thermal oxide dielectric integrity," IEEE Electron Device Lett., vol EDL-7, p.506, 1986 [18] R. M. Andersson and D. R. Kerr : J. Appl. Phys. 48 (1977) 4834 [19] E.A. Irene, E. Tierney, "A viscous flow model to explain the apperarance of high density thermal SiO2 at low oxidation temperature, " J, Electrochem. Soc., vol.129, P.2594, 1982 [20] N. A. Dumin, D. J. Dumin "Effects of nitrogen Incorporation During Growth on Thin Oxide Wearout and Breakdown", Solid-State Electronics, vol.38, p1161, 1995 [21] C. Y. Chen, M. J. Jeng, "Rapid Thermal postoxidation anneal engineering in thin gate oxides with Al gates," IEEE Transaction on Electron Devices., vol. 45, p247, 1998 [22] R. M. Anderson and D. R. Kerr, "Evidence for surface asperity mechanisn of conductivity in oxide grown on polycrystalline silicon," J. Appl. Phys., vol.48 p.4834, 1977 [23] C. Y. Wu and C.F. Chen: J. Appl. Phys. Lett., vol.50, p1167, 1987 [24] L. Faraone, R. D. Vibronek, "Characterization of thermally oxidized n+-polycrystalline silicon," IEEE Transaction on Electron Devices., vol.32, p577,1985 [25] L. Faraone, G. Harbeke,"Surface roughness and electrical conduction of oxide/polysilicon interfaces," J. Electrochem.Soc., vol.133, p1410,1986 [26] E. A. Irene, E. Tierny :J. Electrochem.Soc. vol.127,p705,1980 [27] T. Kubota, K. Ando : IEEE/IRPS p.12, 1996 [28] S. Holland and C. Hu, "Correlation between breakdown and process induced positive charge trapping in thin thermal SiO2," J. Electrochem. Soc., vol. 133, p.1705, 1986
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