(3.239.159.107) 您好!臺灣時間:2021/03/08 21:20
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:鍾昇鎮
研究生(外文):Chung Shen-Chen
論文名稱:表面通道P型金氧半場效電晶體中以新閘極製程抑制硼穿透效應之研究
論文名稱(外文):Suppression of Boron Penetration Effects in a New Process for Surface-Channel PMOSFETs
指導教授:施敏施敏引用關係
指導教授(外文):S. M. Sze
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:中文
論文頁數:31
中文關鍵詞:P型金氧半場效電晶體硼穿透效應
外文關鍵詞:PMOSFETsBoron Penetration Effects
相關次數:
  • 被引用被引用:0
  • 點閱點閱:193
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在CMOS 元件進入深次微米後,以P+型多晶矽製造表面通道P型金氧半場效電晶體是無法避免的。然而,在製作P+型多晶矽和源極汲極離子佈植時所用的硼原子,在佈植之後會穿透閘極氧化層,甚而進入矽底層,造成臨界電壓的不穩定和降低氧化層的可靠性;再者,為了要製作超淺接面,一般都以BF2做離子佈植,而當中的氟原子卻會使硼穿透的效應更加的嚴重。
在本論文中,提出一個新的製作場效電晶體的閘極結構,方法是在製作P+型多晶矽閘極時,以硼離子源代替一般製程的氟化硼 (BF2) 離子源,但是在源極和汲極extension 的離子佈植源還是用BF2,所以還是保有淺接面,主要的目的是讓閘極中沒有氟離子的存在,可以防止因氟離子而增加的硼穿透效應。
結果顯示,在提出的新結構中,氧化介電層的品質獲得明顯的改善、短通道效應減少。另外,也對此結構的元件與一般的元件做熱載子效應的比較,也顯示出此一新的結構,也有較佳的熱載子可靠性。

For deep sub-micro CMOS devices, the p+-polysilicon gate used to achieve surface-channel p-MOSFET becomes indispensable. However, boron atoms implanted into polysilicon gate will penetrate through the gate oxide into Si substrate and alter the channel doping. This, in turn, causes instability of threshold voltage and reduces the oxide reliability. For ultra shallow junctions, BF2 has been employed as an implantation species, but this will enhance boron diffusion through the thin gate oxide. In this dissertation, we use the method of a new method for boron implantation without fluorine atoms. It is to use boron implantation instead of BF2 to form the p+-polysilicon gate. The results show that the oxide quality is improved. The new processing devices exhibit superior characteristics. Furthermore, the short-channel effect, especially the hot-carrier reliability, has also been improved.

Abstract (Chinese)…………………………………………..……..…I
Abstract (English)………………………………………………..…II
Acknowledgment (Chinese)……………………………………..…III
Contents…………………………………………………………....IV
Figure Captions…………………………………………………….V
Chap. 1 Introduction………………………………………….….…1
1.1 General Background…………………………………..1
1.2 Motivation……………………………………………..2
1.3 Organization of the Thesis…………………………….4
Chap. 2 Experiments………………………………………………..6
2.1 Introduction…………………………………………….6
2.2 Vertical Furnace with HF-Vapor Cleaning……………7
2.3 The Fabrication of PMOSFET………………………..7
2.3.1 Capacitor……………………………………….7
2.3.2 Transistor………………………………………8
2.4 The Measurement Techniques……………………….12
Chap. 3 Characterization of The New Gate Structure Transistors and
Capacitors…………………………………………………13
3.1 Gate Oxide Thickness Determination……………….13
3.2 Performance of the 2.5 nm Gate Oxide Transistors and Capacitors……………………………………………14
3.3 New Poly-Gate Structure to Suppress Boron
Penetration……………………………………………15
3.3.1 Oxide Quality……………………………….15
3.3.2 Characteristics of PMOSFET……………….16
3.4 Summary……………………………………………17
Chap.4 Hot-Carrier Reliability……………………………………..18
4.1 Introduction………………………………………….18
4.2 Experiment and Procedure…………………………..19
4.3 Results and Discussion………………………………21
4.4 Summary……………………………………………..22
Chap.5 Conclusions………………………………………………….23
References……………………………………………………………24
Vita

[1] G. A. Saihalasz, M. R. Wordeman, D. P. Kern, E. Ganin, S. Rishton, D. S. Zicherman, H. Schmid, M.R. Polcari, H.Y. Ng, P. J. Restle, T. H. P. Chang, and R.H. Dennard, "Design and Experimental Technology for 0.1-um Gate Length Low-Temperature Operation FET's," IEEE Electron Device Lett. vol. EDL-8, p. 463, (1987).
[2] Y. Taur, S. Cohen, S. Wind, T. Lii, C. Hsu, D. Quinlan, C. Chang, D. Buchanan, P. Agnello, Y. Mii, C. Reeves, A. Acovic, and V. Kesan, "High Transconductance 0.1 um PMOSFET," in IEDM Tech. Dig. p.901, (1992).
[3] K. F. Lee, R. H. Yan, D. Y. Jeon, Y. O. Kim, D. M. Tennant, E. H. Westerwick, K. Early, G. M. Chin, M. D. Morris, R. W. Johnson, T. M. Liu, R. C. Kistler, A. M. Voshchenkov, R. G. Swartz, and A. Ourmazd, ?.1 um p-channel MOSFETs with 51 GHz ft," in IEDM Tech. Dig.,p. 1012, (1992).
[4] K. M. Cham, and S. -Y. Chiang, "Device Design for the Submicrometer p-Channel FET with n+ Polysilicon Gate," IEEE Trans. Electron Devices, vol. ED-31, p.964, (1984).
[5] G. J. Hu, and R. H. Bruce, "Design Tradeoffs Between Surface and Buried Channel FET's," IEEE Trans. Electron Devices, vol. ED-32, p. 584, (1985).
[6] R. R. Troutman, "VLSI Limitations from Drain-Induced Barrier Lowering," IEEE Trans. Electron Devices, vol. ED-26, p.461, (1979).
[7] M. J. Van der Tol, and S. G. Chamberlain, "Drain-Induced Barrier Lowering in Buried-Channel MOSFET's," IEEE Trans. Electron Devices, vol. ED-40, p.741, (1993).
[8] L. C. Parrillo, L. K. Wang, R. D. Swenumson, R. L. Field, R. C. Melin, and R. A. Levy, "Twin-Tub CMOS Ⅱ-An Advanced VLSI Technology," in IEDM Tech. Dig. p. 706, (1982).
[9] G. J. Hu, C. Y. Ting, Y. Taur, and R. H. Dennard, "Design and Fabrication of P-Channel FET for 1-um CMOS Technology," in IEDM Tech. Dig. p. 710, (1982).
[10] Y. Taur, G. J. Hu, R. H. Dennard, L. M. Terman, C. -Y. Ting, and K. E. Petrillo, "A Self-Aligned 1-um-Channel CMOS Technology with Retrograde n-Well and Thin Epitaxy," IEEE Trans. Electron Devices, vol. ED-32, p.203, (1985).
[11] S. Odanaka, M. Fukumoto, G. Fuse, M. Sasago, T. Yabu, and T. Ohzone, "A New Half-Micrometer P-Channel MOSFET with Efficient Punchthrough Stops," IEEE Trans. Electron Devices, vol. ED-33, P. 317, (1986).
[12] S. -Y. Chiang, K. M. Cham, and R. D. Rung, "Optimization of Sub-Micron p-Channel FET structure," in IEDM Tech. Dig. p.534, (1983).
[13] M. Miyake, T. Kobayashi, and Y. Okazaki, "Sub-Quarter-Micrometer Gate Length p-Channel MOSFET's with Shallow Boron Counter-Doped Layer Fabricated Using Channel Preamorphization," IEEE Trans. Electron Devices, vol. ED-37, p. 2007, (1990).
[14] Y. Toyoshima, T. Eguchi, H. Hayashida, and K. Hashimoto, "Novel Shallow Counter Doping Process and High Performance Buried Channel PMOSFET Using Boron Diffusion Through Oxide," in Symp.on VLSI Technology, p. 111, (1991)
[15] J. R. Pfiester, J. D. Hayden, H. C. Kirsch, H. -H. Tseng, and U. Ravaioli, "An Ultra-Shallow Buried-Channel PMOSFET Using Boron Penetration," IEEE Trans. Electron Devices, vol. ED-40, P. 207, (1993).
[16] T. Yoshitomi, M. Saito, H. Oguma, Y. Akasaka, M. Ono, H. Nii, Y. Ushiku, H. Iwai, and H. Hara, "Ultra-Shallow Buried-Channel P-MOSFET with Extremely High Transconductance," in Symp. on VLSI Technology, p.99, (1993).
[17] P. S. -T. Chang, Y. Kohyama, M. Kakuma, A. Sudo, Y. Asao, J. Kumagai, F. Matsuoka, H. Ishiuchi, and S. Sawada, "High Performance Deep Submicron Buried Channel PMOSFET Using P+ Poly-Si Spacer Induced Self-Aligned Ultra Shallow Junctions," in IEDM Tech. Dig. p. 905, (1992).
[18] J. Y. -C. Sun, Y. Taur, R. H. Dennard, and S. P. Klepner, "Submicrometer-Channel CMOS for Low-Temperature Operation," IEEE Trans. Electron Devices, vol. ED-34, p. 19, (1987).
[19] K. Tanaka, and M. Fukuma, "Design Methodology for Deep Submicron CMOS," in IEDM Tech. Dig. p. 628, (1987).
[20] B. Ei-Kareh, W. W. Abadeer, W. R. Tonti, "Design of Submicron PMOSFETs for DRAM Array Applications," in IEDM Tech. Dig. p. 370, (1991).
[21] M. -L. Chen, W. T. Cochran, T. S. Yang, C. Dziuba, C. -W. Leung, W. Lin, and
W. Jungling, "Constraints in P-Channel Device Engineering for Submicron
CMOS Technologies," in IEDM Tech. Dig., p. 390, (1988).
[22] Y. Hiruta, K. Maeguchi, and K. Kanzake, "Impact of Hot Electron Trapping on Half Micron PMOSFETs with P+ Poly Si Gate," in IEDM Tech. Dig., p. 718, ( 1986 ).
[23] C. C. -H. Hsu, D. -S. Wen, M. R. Wordeman, Y. Taur, and T. H. Ning, "A Comprehensive Study of Hot-Carrier Instability in P- and V-Type Poly-Si Gated MOSFET's," IEEE Trans. Electron Devices, vol. ED-41, p. 675, (1994).
[24] F. Matsuoka, H. Iwai, H. Hayashida, K. Hama, Y. Toyoshima, and K. Maeguchi, "Analysis of Hot-Carrier-Induced Degradation Mode on pMOSFET's," IEEE Trans. Electron Devices, vol. ED-37, p. 1487, (1990)
[25] M. P. Brassington, and R. R. Razouk, "The Relationship Between Gate Bias and Hot-Carrier-Induced Instabilities in Buried- and Surface-Channel PMOSGET's," IEEE Trans. Electron Devices, vol. ED-35, p. 320, (1988).
[26] I. Kato, H. Horie, M. Taguchi, and H. Ishikawa, "Mechanism of Hot Electron Trapping on PMOSFET with P+ Polysilicon Gate," in IEDM Tech. Dig., p. 14, (1988).
[27] J. Y. -C. Sun, C. Wong, Y. Taur, and C. -H. Hsu, "Study of Boron Penetration Through Thin Oxide with P+ -Polysilicon Gate," in Symp. on VLSI Technology, p. 17, (1989).
[28] J. R. Pfiester, F. K. Baker, T. C. Mele, H. -H. Tseng, P. J. Tobin, J. D. Hayden, J. W. Miller, C. D. Gunderson, and L. C. Parrillo, "The Effects of Boron Penetration on P+ Polysilicon Gated PMOS Devices," IEEE Trans. Electron Devices, vol. ED-37, p. 1842, (1990).
[29] J. M. Sung, and C. Y. Lu, "A Comprehensive Study on P+ Polysilicon-Gate MOSFET's Instability with Fluorine Incorporation," IEEE Trans. Electron Devices, vol. ED-37, p. 2312, (1990).
[30] C. Y. Wong, J. Y. -C. Sun, Y. Taur, C. S. Oh, R. Angelucci, and B. Davari, "Doping of N+ and P+ Polysilicon in a Dual-Gate CMOS Process," in IEDM Tech. Dig., p. 238, (1988).
[31] C. Y. Lu, J. M. Sung, H. C. Kirsch, S. J. Hillenius, T. E. Smith, and L. Manchanda, "Anomalous C-V Characteristics of Implanted Poly MOS Structures in n+/ p+ Dual-Gate COMS Technology," IEEE Electron Devicde Lett., vol. EDL-10, p. 192, (1989).
[32] A. S. Grove, O. Leistiko, Jr., and C. T. Sah, "Redistribution of Acceptor and Donor Impurities during Thermal Oxidation of Silicon," J. Appl. Phys., vol. 35, p. 2695, (1964).
[33] C. Y. Wong, and F. S. Lai, "Ambient and Dopant Effects on Boron Diffusion in
Oxides," Appl. Phys. Lett., vol. 48, p. 1658, (1986).
[34] L. Manchanda, "Hot-Electron Trapping and Generic Reliability of P+ Polysilicon/SiO2/Si Structures for Fine-Line CMOS Technology," in IEEE Int. Reliability Phys. Symp. Tech. Dig., p. 183, (1986).
[35] H. Nakayama, Y. Osada, and M. Shindo, "Room Temperature Instabilities of P-Channel Silicon Gate MOS Transistors," J. Electrochem. Soc., vol. 125, p. 1302, (1978).
[36] L. Dori, J. Sun, M. Arienzo, S. Basavaiah, Y Taur, and D. Zichermann, "Very Thin Nitride/Oxide Composite Gate Insulatro for VLSI CMOS," in symp. On VLSI Technology, p. 25, (1987).
[37] J. S. Cable, R. A. Mann, and J. C. S. Woo, "Impurity Barrier Properties of Reoxidized Nitrided Oxide Films for use with p+-Doped Polysilixon Gates, " IEEE Electron Device Lett., vol. EDL-12, p. 128, (1991).
[38] G. Q. Lo, and D. -L. Kwong, "The Use of Ultrathin Reoxidezed Nitride Gate Oxide for Suppression of Boron Penetration in BF2+-Implanted Polysilicon Gated p-MOSFET'S," IEEE Electron Device Lett., vol. EDL-12, p. 175 (1991)
[47] H. Hawing, W. Ting, D. -L. Kwong, and J. Lee, "Electrical and Reliability Characteristics of Ultrathin Oxynitride Gate Dielectric Prepared by Rapid Thermal Processing in N2O," in IEDM Tech. Dig. p.421, (1990).
[48] A. Uchiyama, H. Fukuda, T. Hayashi, T. Iwabuchi, and S. Ohno, "High Performance Dual-Gate Sub-Halfmicron CMOSFETs with 6 nm-thick Nitrided SiO2 Films in an ambient," in IEDM Tech. Dig., p. 425, (1990)
[49] H. S. Momose, T. Morimoto, Y. Ozawa, M. Tsuchiaki,M. Ono, K. Yamabe, and H. Iwai, "Very Lightly Nitrided Oxide Gate MOSFETs for Deep-submicron CMOS Devices," in IEDM Tech. Dig., p.359, (1991).
[50] A. B. Joshi, J. Ahn, and D. L. Kwong, "Oxynitride Gate Dielectrics for p+-Polysilicon Gate MOS Devices," IEEE Electron Device Lett., vol. EDL-14, p. 560, (1993).
[51] Z. J. Ma, J. C. Chen, z. H. Liu, J. T. Krick, Y. C. Cheng, C. Hu, and P. K. Ko, "Suppression of Boron Penetration in P+ Polysilicon Gate P-MOSGET's Using Low-Temperature Gate-Oxide N2O Anneal," IEEE Electron Device Lett., vol. EDL-15, p. 109, (1994).
[52] H. -H. Tseng, P. J. Tobin, F. K. Baker, J. R. Pfiester, K. Evans, and P. L. Fejes, "The Effect of Silicon Gate Microstructure and Gate Oxide Process on Threshold Voltage Instabilities in p+-Gate p-Channel MOSFET's with Fluorine Incorporation," IEEE Trans. ElectronDevices, vol. ED-39, p. 1687, (1992).
[53] S. L. Wu, c. L. Lee, and T. F. Lei, "Suppression of Boron Penetration into an Ultra-Thin Gate Oxide (≦ 7nm) by Using a Stacked-Amorphous-Silicon(SAS) Film," in IEDM Tech. Dig., p. 329, (1993).
[54] M. Kida, Y. Shida, J. Kawaguchi, and Y. Kaneko, "Improving Gate Oxide Intrgrity in p+ pMOSFET by Using Large Grain Size Polysilicon Gate," in IEDM Tech. Dig., p. 471, (1993).
[55] T. Hori, H. Iwasaki, Y. Naito, and H. Esaki, "Electrical and Physical Characteristics of Thin Nitrided Oxides Prepared by Rapid Thermal Nitridation," IEEE Trans. Electron Devices, vol. ED-34, p. 2238, (1987).
[56] H. S. Momose, s. Kitagawa, K. Yanabe, and H. Iwai, "Hot Carrier Related Phenomena for n- and p-Channel MOSFET's with Nitrided Gate Oxide by RTP," in IEDM Tech. Dig., p. 267, (1989).
[57] A. T. Wu, T. Y. Chan, V. Murali, S. W. Lee, j. Nulman, and M. Garner, "Nitridation Indeed Surface Donor Layer in Silicon and It's Inpact on the Characteristics of n- and p-Channel MOSFET's, " in IEDM Tech. Dig., p. 271,
(1989).
[58] H. Hori, "Deep-Submicron Nitrided-Oxide CMOS Technology for 3.3-V Operation," in IEDM Tech. Dig., p. 837, (1990).
[59] T. Hori, and H. Iwasaki, "Ultra-Thin Re-Oxidation Nitrided-Oxides Prepared by Rapid Thermal Processing," in IEDM Tech. Dig., p. 570, (1987).
[60] J. Ahn, and D. L. Kwong, "Electrical Properties of MOSFET's with N2O Nitrided LPCVD SiO2 Gate Dielectrics," IEEE Electron Device Lett., vol. EDL-13, p. 494 (1992).
[61] J. R. Pfiester, L. C. Parrillo, and F. K. Baker, "A Physical Model for Boron Penetration Through Thin Gate Oxides from p+ Polysilicon Gates," IEEE Electron Device Lett., vol. EDL-11, p. 247, (1990)
[62] H. -H. Tseng, M. Orlowski, P. J. Tobin, and R. L. Hance, "Fluorine Diffusion on
a Polysilicon Grain Boundary Network in Relation to Boron Penetration from P+
Gates," IEEE Electron Device Lett., vol. EDL-13, p. 14, (1992).
[63] K. Schuegraf et. Al, "Hole injection SiO2 breakdown model for " IEEE Trans.
Electron Devices, Vol.41, p. 761, 1994.
[64] M. Lenzlinger et al., "Fowler-Nordhiem tunnelling into thermally grown SiO2"J.
Appl. Phys., Vol.40, p.278 , 1969.
[65] K. Schuegraf et al, "Ultra-Thin silicon dioxide leakage current and scaling limit",
VLSI Tech, p.18, 1992.
[66] J. R. Pfiester et al., "The Effects of Boron Penetration on P+ Polysilicon Gated
PMOS Devices," IEEE Trans. Electron Devices, vol. ED-37, p. 1842, 1990.
[67] J. M. Sung et al., "A Comprehensive Study on p+ Polysilicon-Gate MOSFET's
Instability with Fluorine Incorporation," IEEE Trans. Electron Devices, vol. ED-
37, p. 2312, 1990.
[68] K. K. Ng et al., "Effects of hot-carrier trapping in n-and p-channel MOSFET's,"
IEEE Trans. Electron Devices, vol. ED-30, p. 871. 1983.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關論文
 
系統版面圖檔 系統版面圖檔