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研究生:楊文杰
研究生(外文):Wen-Jei Yang
論文名稱:淺凹槽隔離深次微米互補金氧半元件窄寬度效應熱載子可靠性的研究
論文名稱(外文):The Width-Dependent Hot Carrier Reliability of Deep-Submicron CMOS with Shallow Trench Isolation
指導教授:莊紹勳
指導教授(外文):Steve S. Chung
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:英文
中文關鍵詞:互補式金氧半元件淺凹槽隔離技術矽上局部氧化隔離技術熱載子退化通道短化效應介面狀態
外文關鍵詞:CMOSFETShallow Trench Isolation (STI)Local Oxidation on Silicon (LOCOS)Hot Carrier DegradationChannel Shortening EffectInterface States
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為了增加積體電路元件的密度,互補式金氧半元件 (CMOS) 的隔離技術愈形重要。近年來,淺凹槽隔離技術(Shallow Trench Isolation)已被廣泛地採用以達此一目的。此外,淺凹槽隔離技術還可改善矽上局部氧化隔離技術 (LOCOS) 的特性,例如次臨限區電流突起 (subthreshold hump) ,鳥嘴 (bird's beak) ,以及場氧化層薄化效應 (field oxide thinning) 等。然而,熱載子可靠度仍是淺凹槽隔離技術元件所面臨的主要問題。
本論文將深入探討淺凹槽隔離之互補式金氧半元件的熱載子退化寬度效應。寬度較窄的元件雖然有較低的熱載子注入,但研究卻顯示窄元件有較大的熱載子退化現象。在P型元件中,吾人根據通道短化效應 (Channel Shortening) 之觀念,提出一套新的模型以解釋此一寬度效應。在熱載子加壓後,通道邊緣的短化會較中央嚴重,所以窄元件表現了較明顯的退化現象。而N型元件中, 可能導因於元件邊緣的機械應力 (Mechanical Stress) ,在通道邊緣介面狀態 (Interface State) 的產生速率較快,而造成了較大的電流退化。

To improve the packing density of integrated circuits, scaling of CMOS isolation become indispensable. Recently, the shallow-trench-isolation (STI) technology has been widely used to achieve this goal. Moreover, STI can improve the subthreshold hump, bird掇 beak, and field oxide thinning effect in LOCOS (Local Oxidation of Silicon). However, hot-carrier effect has been be a major reliability issue in a STI device.
In this thesis, width dependent hot-carrier degradation of shallow-trench-isolated MOSFET's is investigated. Smaller hot carrier injection is observed in a narrower device. However, it is shown that a narrower device causes larger drain current degradation under the same stress condition. A new model is then proposed to explain the width dependent degradation. This model is based on the channel shortening concept which can be used to explain the width dependent hot carrier degradation in PMOSFET's. It was found that the channel shortening length after device stress becomes larger at the edge of a PMOFET. Thus, a narrower PMOSFET has larger effective channel shortening length and hence a larger current degradation after stress. In the case of NMOSFET's, enhanced interface state generation was found at the STI edge. This may be due to the mechanical stress at the device edge. So, the average amount of interface states and current degradation in a narrower NMOSFET is larger after hot-carrier stress.

Contents
Chinese Abstracti
English Abstractiii
Acknowledgementsv
Contentsvi
Figure Captionsviii
Chapter 1Introduction1
Chapter 2Device Fabrication and Basic I-V Characteristics3
2.1Introduction3
2.2Device Fabrication Process3
2.3Basic I-V Characteristics4
Chapter 3Width Dependent Hot Carrier Degradation in PMOSFET掇12
3.1Introduction12
3.2Experimental Results12
3.2.1 Width Dependent Drain Current Degradation12
3.2.2 Comparison of the Impact Ionization Rate and the Gate Injection
Current 14
3.2.3 Electron Trapping Efficiency in Gate Oxide20
3.3Hot-Carrier Degradation Mechanism in Narrow Width
PMOSFET掇20
3.3.1Channel Shortening Effect23
3.3.2Width Position Dependent Channel Shortening Effect25
3.4Summary27
Chapter 4Width Dependent Hot Carrier Degradation in NMOSFET掇32
4.1Introduction32
4.2Experimental Results32
4.2.1Width Dependent Drain Current Degradation32
4.2.2Comparison of the Impact Ionization Rate35
4.3Hot-Carrier Degradation Mechanism in Narrow Width
NMOSFET掇 41
4.4Summary41
Chapter 5Conclusion46
References47

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