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研究生:陳柏升
研究生(外文):Po-Shen Chen
論文名稱:多層印刷電路板中地彈雜訊的分析
論文名稱(外文):The Analysis of Ground Bounce Problem in Multilayer Printed Circuit Boards
指導教授:吳霖
指導教授(外文):Lin-Kun Wu
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:中文
論文頁數:58
中文關鍵詞:多層印刷電路板地彈雜訊有限差分法非理想去耦合電容
外文關鍵詞:Ground BounceMultilayer Printed Circuit BoardsFDTD
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本文以時域-有限差分法 (FDTD) 探討多層印刷電路板中高速切換元件的切換速度,以及其與板間電容和去耦合電容之間的相互作用,對 Ground Bounce 的影響。基於考量電腦計算資源上的限制,印刷電路板的層數將設定為四層,其分佈狀況為:Signal Plane---Ground Plane---Power Plane---Signal Plane。切換元件與去耦合電容皆平置於電路板的最上層,其兩端接腳則經由vias 分別與第二層的Ground Plane 和第三層的Power Plane 連接。層與層之間的介質為FR-4 材質。由於圓柱形 vias 的模擬較為複雜,為簡化 FDTD 的複雜度,我們將先忽略實際的 vias,亦即原本位於最上 (或最下) 信號層的零件將被存在於 Power 和 Ground 層之間的數值元件模型取代。再加上尺寸的假設,我們只需考量平行平板內部任一與板面平行的平面上的二維電磁場問題。在本文的分析方法下,我們可獲得: 充放電電壓擾動在 Power/Ground Planes 上的分佈狀況、在距干擾源一單位晶格的四周加入四個理想去耦合電容形成一電容牆,可使去耦合電容達到最大的防堵效果,且所加的去耦合電容越大所能阻止的外漏現象越多、當加入的去耦合電容總值相同時,運用電容牆作防堵效果比用單一電容來得顯著、以及把實際的非理想去耦合電容因接腳電感的存在而無法瞬間 充放電的特性以接腳電感來表示時,加入的接腳電感值越大,瞬間充放電的能力越差,便使得防止外漏的能力變差。
FDTD is the best method to solve the ground bounce in PCBS.
摘要
目錄
圖目錄
第一章 簡介
第二章 研究方法
2-1 問題敘述
2-2 馬克斯威爾方程式的有限差分近似
2-3 穩定規範
2-4 激發源的選定
2-5 集總元件的 FDTD 數值模型
2-6 理想去耦合電容的 FDTD 數值模型
2-7 非理想去耦合電容的 FDTD 數值模型
第三章 數值結果及討論
3-1 收斂測試
3-2 激發源的影響
3-3 空板效應
3-4 理想去耦合電容效應
3-5 非理想去耦合電容效應
第四章 結論
參考文獻
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