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研究生:法正宏
研究生(外文):Fa Cheng Hung
論文名稱:高速乙太網路接收機中管線化決策回授型等化器之ASIC設計
論文名稱(外文):An ASIC Design of the Pipelined DFE for 100BASE-TX Ethernet Transceivers
指導教授:吳文榕
指導教授(外文):Wen-Rong Wu
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:英文
論文頁數:85
中文關鍵詞:高速乙太網路管線化設計決策回授型等化器等化器
外文關鍵詞:100BASE-TXFast EthernetDecision feedback EqualizerEqualizerPipelined DesignVHDLASIC
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在100BASE-TX接收機設計中,以數位訊號處理(DSP)技術為基礎的設計理念,逐漸替代了傳統類比式的想法。對數位化的實現方式而言,其最大的挑戰在於如何滿足高速處理速度的要求。在這篇論文中,我們將應用架構(architecture)與演算法則(algorithm)的轉換技術,來建構一個高速等化器。而有關於硬體實現方面的議題,如硬體面積的節省等,也會一併提出討論。最後,我們使用硬體描述語言VHDL與硬體定點格式觀念,去實現所提出的設計構想。而經效能驗證後,其結果證實了我們的設計構想,在100BASE-TX應用上的可行性。

The DSP-based design has gradually replaced the conventional analog approach in the 100BASE-TX transceiver. The main challenge for the the digital implementation is the requirement of high speed processing rate. In this thesis, the architecture and algorithm transformation techniques are used to construct a high speed equalizer. The implementation issues such as hardware saving are also be discussed. The fixed-point format of our design has been implemented with VHDL language. The result of
performance verification has proven the feasibility of our design in the 100BASE-TX application.

1 INTRODUCTION
2 The PHY Transceiver for 100BASE-TX
2.1 The 100BASE-TX Physical Protocol
2.2 Adaptive Filter
2.3 Baseline Wander
2.4 The architecture of PHY Transceiver
3 Pipelined Adaptive Decision Feedback Equalizer
3.1 Linear Equalizer
3.2 Decision Feedback Equalizer
3.3 Architecture Transformation Techniques
3.4 Algorithm Transformation techniques
3.5 Pipelined Adaptive DFE
3.6 MATLAB Simulation
4 The ASIC Design of the Pipelined DFE
4.1 Architecture Style
4.2 Architecture Complexity
4.3 Fixed-point Implementation
4.4 Digital Precision of Adaptation Algorithm
4.5 Hardware Reduction
4.6 The Performance Verification
5 Conclusion

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