在此篇論文中由數位式鎖相迴路(digital phase locked loop)的理論分析，設計出具有可調適性的迴路頻寬增益，以利於起始時快速追蹤相位，然後再減小迴路頻寬增益，以減少信號擾動。本文中，對於一階探討了最佳化的演算法，然後再改進為次佳化、近似法以期能使用於數位電路的實際應用。並就此類的演算法與非可調適性的演算法，對相位追蹤做一相對應的比較，並顯現信號擾動減少的情形。然後在二階的迴路中，討論了最小均方差(MMSE)及遞迴平方差(RLS)的演算法，再與非可調適性的二階作一比較。最後對於載波回復的應用，探討在瑞雷衰減及都卜勒平移的影響下，最小均方差、遞迴平方差及非可調適性演算法的效能。

目錄i
圖目索引ii
第一章 緒論1
1.1數位式鎖相迴路簡介1
1.2研究動機3
1.3各章內容提要4
第二章 雙迴路數位鎖相迴路6
2.1一階數位鎖相迴路最小均方差演算法6
2.2二階數位鎖相迴路最小均方差演算法10
2.3二階數位鎖相迴路遞迴最小平方差演算法13
第三章 電腦模擬18
3.1一階數位鎖相迴路18
3.2二階數位鎖相迴路21
3.3行動通訊環境23
第四章 結論45
參考文獻46

[1] F. M. Gardner, and J. D. Barker, Simulation Techniques: models of communication signals and processes, New York, John Wiley & Sons Inc., 1997.
[2] I. S. Xezonakis, and M. S. Sangriotis, “Algorithm for the construction of an all-digital early-late BPSK/QPSK symbol synchronizer,” Int. J. Electron., 1991, 70, 1, pp.1-10
[3] C. A. Pomalaza-Raez, “Analysis of an all-digital data-transition tracking loop”, IEEE Trans., 1992, AES-28,(4), pp.1119-1127
[4] I. S. Xezonakis, and M. S. Sangriotis, “An all digital Costas loop-like PLL circuit with a wide locking range”, Int. J. Electron., 1991, 71, (6), pp.951-965
[5] A. N. D’Andrea, and F. rousso, “Switched polarity DPLL’s for PSK demodulation’. Proc. INFO II Patras Greece, 1979, pp. 253-260
[6] M. S. Sangriotis, and I. S. Xezonakis, “Digital Costas loop-like PLL for carrier recovery of a QPSK signal”, Electronics Letters, 1993, vol.29, no.10, pp.897-899
[7] W. C. Liney and C. M. Chie, “A survey of digital phase locked loop,” Proceedings of IEEE, 69, 4(Apr. 1981), pp. 410-431.
[8] R. E. Best, Phase-locked loops: theory, design, applications, 2nd, New York, McGraw-Hill, 1993.
[9] R. W. Chang, and R. Srinivasagopalan, “Carrier recovery for data communication systems with adaptive equalization,” IEEE Trans. Comm., vol. COM-28, pp. 1142-, Aug. 1980.
[10] A. Aghamohammadi, H. Meyr, and G. Asheid, “Adaptive synchronization and channel parameter estimation using extended Kalman filter,” IEEE Trans. Comm., vol. 37, pp. 1212-1219, Nov. 1989.
[11] P. F. Driessen, “DPLL bit synchronizer with rapid acquisition using adaptive Kalman filtering techniques,” IEEE Trans. Comm., vol. 42, pp. 2673-2675, Sept. 1994.
[12] B. Kim, “Dual-loop DPLL gear-shifting algorithm for fast synchronization,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 44, pp. 577-586, July 1997.
[13] W. Hsu, F. Chui, and D. A. Hodges, “An acoustic echo canceler,” IEEE J. Solid-State Circuits, vol. 24, pp. 1639-1646, Dec. 1989.
[14] B. Kim, “High speed clock recovery in VLSI using hybrid analog/digital techniques,” Memo. UCB/ERL M90/50, June 6, 1990.
[15] EIA/TIA/IS-54-A, “Dual-mode Mobile Station — Base Station Compatibility Standard” Electronic Industries Association, March, 1991
[16] C. -L. Liu and K Feher, “Bit eeror rate performance of pi/4-DQPSK in a frequency-selective fast Rayleigh fading channel,” IEEE Trans. Veh. Technol., vol. 40, pp. 558-568, Aug. 1991
[17] W. C. Liney and M. K. Simon, “Carrier synchronzation and detection of polyphase signals,” IEEE Trans. Comm., vol. COM-20, pp. 441-454, June 1972