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研究生:王照勳
研究生(外文):Jaw-Shiun Wong
論文名稱:適用於無線資料進接系統之CMOS類比前端電路特性化及設計
論文名稱(外文):CMOS Analog Front-End Characterization and Design for Wireless Data Access System
指導教授:周世傑周世傑引用關係汪重光汪重光引用關係
指導教授(外文):Shyh-jye JouChorng-kuang Wang
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:英文
論文頁數:95
中文關鍵詞:射頻電路高頻類比電路中頻電路多相位鏡像消去濾波器箝制放大器
外文關鍵詞:RFHigh Frequency Analog CircuitIFPolyphase Image Reject FilterLimiing Amplifier
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隨著可攜式個人無線通訊的蓬勃發展,低消耗功率、低成本、高整合度的電路成為未來的趨勢。目前的通訊系統電路多是採多晶片、多製程的方式來製作,利用較好元件特性的砷化鎵(GaAs)或雙載子接面電晶體(BJT)來製作較低雜訊、高功率的射頻前端電路,而互補式金氧半場效應電晶體(CMOS)則多是應用於基頻電路或數位處理電路。隨著互補式金氧半場效應電晶體(CMOS)製程技術不斷的提昇,可以應用的頻率也越來越高,再加上適當的架構選擇,使得整個接收機的射頻類比前端電路可以在互補式金氧半場效應電晶體(CMOS)製程實現,並與低頻的電路或是數位處理電路整合在單一晶片中。本論文的研究目標在於利用互補式金氧半場效應電晶體(CMOS)製程,來實現一低工作電壓、低消耗功率、高整合度的接收機射頻類比前端電路。
在本論文中,首先針對各個不同的接收機架構作一番討論,這裡採用了多相位鏡像消去法(Polyphase Image Reject Receiver)的方式來實現我們的接收機。接下來對於一些達到系統要求效能的設計考量作一些探討,並用在一個900MHz 展頻無線電話的射頻類比前端接收機設計。從整合性的設計觀點來探討評估這個系統每一個部份的特性並作為電路設計之依據。
整個類比前端電路的部份包括兩個利用臺灣積體電路公司0.6微米SPTM互補式金氧半場效應電晶體(CMOS)製程所製造的晶片;射頻前端的部份面績為1800毫米乘上1800毫米,由一個低雜訊放大器,兩個降頻的混波器,一個多相位濾波器,兩組放大功率的補償電路,和兩個輸出的緩衝放大級所組成。總共提供了43.7 dB的電壓功率放大,7.9dB的雜訊指數,和 -43dB的鏡像相消比,在2伏特的電壓源下共消耗170毫瓦。另一個晶片為中頻解調之限制放大器和一個接收訊號強度指示器,提供了80dB的電壓功率放大,和-75dB的敏感度,和小於正負1dB接收訊號強度指示器的線性度,在2伏特的電壓源下共消耗了27毫瓦,並藉由實際量測結果來驗證設計功能無誤。

Since the rapid development of the CMOS technology, a RF analog front-end receiver
can integrate on a single chip. This thesis introduces a highly integrated RF receiver and
IF analog signal processor for Spread Spectrum Telephony system and several function
design methodologies. This system composes of a low noise amplifier, a down conversion
mixer, an LO input buffer, a first stage buffer, a polyphase filter, a second stage buffer,
an output driver, and a 110.5MHz limiting amplifier with a receiver strength signal
indicator (RSSI). It receives the 900MHz desired high frequency signal, then translates
to 110.5MHz IF, next through polyphase filter to filter out the negative sequence image
signal, and drives to external high quality SAW filter to select the desired channel signal.
Finally inputs to the limiting amplifier, and output is the digital-like signals, which are
only high and low two level signals.
The whole receiver is implemented by using the TSMC 0.6um SPTM standard
CMOS technology and divided into two chips: a 900MHz RF analog frond-end re-
ceiver and a 110.5MHz IF signal processor. The 900MHz RF front-end has 43.7dB
cascaded voltage gain, 7.9 dB noise figure referred to the antenna and -43dB image
reject. The total RF front-end power consumption is about 170mW. The chip area is
1800um X 1800um. And the 110.5MHz IF signal processor has 80dB voltage gain, -
75dBm sensitivity, and the RSSI linearity is less then +/- 1dB. The IF signal processor
power dissipation is about 27mW. The chip area is 1800um X 1800um. The experimental
results of this project are also demonstrated to testify the analysis of the discussion in
this thesis.

Contents
List of Tables vi
List of Figures vii
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Receiver Architecture 4
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 General Concern for Receiver . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Review of Receiver Architectures . . . . . . . . . . . . . . . . . . . . . . 7
2.3.1 Heterodyne Receiver . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.2 Heterodyne Receiver Architecture . . . . . . . . . . . . . . . . . . 9
2.4 Image-Reject Receiver Technique . . . . . . . . . . . . . . . . . . . . . . 12
2.4.1 Hartley Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.2 Weaver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.3 Polyphase Architecture . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 RF Front-End Designs 19
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.1 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.3 Gain Compression . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.4 Third-Order Intermodulation . . . . . . . . . . . . . . . . . . . . 22
3.2.5 Desensitization and Blocking . . . . . . . . . . . . . . . . . . . . . 24
3.3 Specification and Design Considerations . . . . . . . . . . . . . . . . . . 24
3.4 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 Low Noise Amplifer 29
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 Integrated Inductors Realization . . . . . . . . . . . . . . . . . . . . . . . 29
4.2.1 Bonding Wire Inductor . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.2 Active Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.3 Spiral Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3 MOSFET Noise, RF model, and Experimental Analysis . . . . . . . . . . 33
4.3.1 Noise In MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3.2 MOSFET RF Model . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3.3 Experimental CMOS Low Noise Amplifier . . . . . . . . . . . . . 36
4.4 Circuit Design and Simulation Results . . . . . . . . . . . . . . . . . . . 37
4.4.1 Input Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4.2 Conversion Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4.3 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5 Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5 Mixer 47
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2 Properties of Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3 Circuit Architecture and Simulation Results . . . . . . . . . . . . . . . . 49
5.3.1 Conversion Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.2 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4 Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6 Polyphase Image Reject 56
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.2 Polyphase System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2.1 Polyphase Network Property . . . . . . . . . . . . . . . . . . . . . 57
6.2.2 Practical Consideration . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3 LO Buffer design and simulation results . . . . . . . . . . . . . . . . . . . 62
6.4 Compensation Amplifier and the Output Driver Design . . . . . . . . . . 63
6.5 Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.6 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7 110MHz IF Signal Processing 71
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.2 Magnitude Control Architecture . . . . . . . . . . . . . . . . . . . . . . . 71
7.3 High Frequency Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . 73
7.3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.3.2 Gain Cell Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.3.3 Offset Cancellation Design . . . . . . . . . . . . . . . . . . . . . . 76
7.3.4 Bandpass Filter and Buffer Design . . . . . . . . . . . . . . . . . 77
7.4 Receive Signal Strength Indicator . . . . . . . . . . . . . . . . . . . . . . 78
7.4.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.4.2 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
8 Conclusion 87
A Testing Consideration 89
A.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.2 RF Front-End Receiver Testing . . . . . . . . . . . . . . . . . . . . . . . 90
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