在本篇論文中，我們提出一個可應用於有線電視上的載波回復電路以及時序回復電路架構，並且將此架構以硬體的方式實現。此架構不只適用於垂直正交振幅調變 (QAM, Quadrature Amplitude Modulation)，同時也適用於殘旁邊帶振幅調變 (VSB, Vestigial Side-band Modulation)。在載波回復電路中，我們採用驟斜率方法 (Steep Gradient Method) 應用於相位檢測器 (Phase Detector) 上，而在時序回復電路中，我們則使用鮑率 (Baud-Rate) 相位檢測器。雖然此兩種方法在硬體時現實並不困難，然而為了要使電路更為簡單，我們另外也採用了方向理論 (Sign Algorithm)，如此，原來電路中的乘法器將可以被二補數電路所取代。除此之外，為了增加載波回復電路的頻率追蹤範圍 (Acquisition Range)，在殘旁邊帶振幅調變模式中，我們另外加入的一個鎖頻迴路 (Frequency Locked Loop)；而在垂直正交振幅調變模式中，我們則加入了一對相位解旋/旋轉電路 (Dero-tator/Rotator Pair) 於載波回復電路之前。如此，依據C語言所架構的系統所得到的結果，此時載波回復電路可以具有100KHz的頻率追蹤範圍。最後，我們將載波回復電路、時序回復電路、鎖頻迴路、數值控制震盪器 (NCO, Numerically Controlled Oscillator) 以及混波器 (Mixer) 以硬體描述語言Verilog來描述，然後以Synopsys做電路的整合與最佳化。根據整合後的結果顯示，整個電路總共需要32,120閘。

In this thesis, an architecture design and hardware implementation for carrier re-covery (CR) and timing recovery (TR) in CATV system are proposed. It is not only suitable for Vestigal SideBand Modulation (VSB) but also suitable for Quadrature Amplitude Modulation (QAM). For CR, a Steep Gradient mothod is used, and for TR, a baud-rate TR is employed in our system. To reduce the hardware complexity, both of them use sign algorithm. Furthermore, to increase the acquisition range of CR, in VSB mode, a Frequency Locked Loop (FLL) is used while in QAM mode, a derota-tor/rotator pair is adopted. As a result, the CR can reach 100KHz acquisition range from simulation results. Finally, the whole design, which consists of a TR, a CR, a FLL, a loop controller, a mixer, and two NCOs, is desribed by Verilog hardware lan-guage and synthesized by Synopsys. From synthesis reports, the total gate counts are 32,120 gates.

1Introduction1
1.1Background1
1.2Motivation2
1.3Thesis Organization3
2Overview and Modification of the CATV Transceiver
Architecture5
2.1Transmitter5
2.2Receiver6
2.3Receiver Enhancement8
2.3.1The Modification in VSB Mode10
2.3.2The Modification in QAM Mode13
2.4Summary19
3Frequency Locked Loop20
3.1FLL20
3.1.1Loop Filter of FLL21
3.1.2Frequency Detector of FLL22
3.2Simulation Results by Matlab and C Code25
3.2.1Filter Design26
3.2.2Steady State Error30
3.3Hardware Implementation33
3.3.1Low Voltage Low Power33
3.3.2Frequency Detector33
3.3.3Simulation Results37
4Carrier Recovery Loop39
4.1Carrier Recovery39
4.1.1Introduction of PLL39
4.1.2Phase Detector Theorem42
4.2Derotator/Rotator46
4.2.1Passband Equalization46
4.2.2Structure of a Derotator/Rotator48
4.3Simulation Results by C Code50
4.3.1Bandwidth Adjustment51
4.3.2Latency of CR Loop52
4.4Hardware Implementation57
4.4.1Phase Detector57
4.4.2Prefilter and Bandwidth Controller58
4.4.3PI-filter59
4.4.4Synthesis Results59
5Timing Recovery62
5.1Phase Detector Theorem62
5.1.1Spectral-Line Method62
5.1.2MMSE Method64
5.1.3Baud-Rate Timing Recovery65
5.2Architecture of TR66
5.3Simulation Results68
6Overall Hardware Implementation72
6.1Overall Circuit Design72
6.1.1Loop Controller73
6.1.2NCO74
6.2Simulation Results75
7Conclusion78
Reference80

[1] F. Van der Putten, M. Trevisan, L. Rysdale, and C. Peterson, "Lower Layer Protocols and Physical Interfaces," DAVIC 1.0 Specifications, Part8, Revision 3.0, May 1995.
[2] M. Chelehmal, "Transmission of Digital HDTV Part 2," Communication Technology, pp. 47-52, Dec. 1992.
[3] D. T. Gall, "Digital Modulation on Coaxial/Fiber Hybrid Systems," Communication Technology, pp.42-45, Jun. 1995.
[4] Brian James, "High Definition Television-Defining The Standard," NCTA Technical Papers, pp. 375-381. 1994.
[5] Ron Lee, Setting the record straight: VSB vs. QAM, "Communication Technology, pp. 37-41, Jun. 1995.
[6] Tony Filanowski, "QAM for Broadband Networks: the Right Choice," Communication Technology, pp. 36,82-85, Jun. 1995.
[7] K. J. Kerpez, "A Comparison of QAM and VSB for Hybrid Fiber/Coax Digital Transmission," IEEE Trans. Broadcasting, vol. 41, NO. 1, pp. 9-16, March 1995.
[8] M. T. Shiue, "Transceiver VLSI Design for High Speed Local Access Modems," PH. D. Thesis, National Central University, 1998.
[9] M. T. Shiue, C. K. Wang, K. H. Huang, and C. I. Huang, "A Dual Mode Digital Transceiver for Both the QAM and VSB Digital Communication System," Taiwan, R.O.C. patent 1998, and U.S.A Patent filed in 1997.
[10] M. T. Shiue, K. H. Huang, C. K. Wang, and Winston I. Way, "A VLSI Architecture Design for Both QAM and VSB Digital CATV Transceiver," TJCOM98, Hsin-Chu, Taiwan, R.O.C., Jan. pp. 20-22, 1998.
[11] A. Cook and J. Stern, "Optical Fiber Access - Perspectives toward the 21st Century," IEEE Commun. Mag., vol. 31, NO. 2, pp. 78-86, Feb. 1994.
[12] D. G. Messerschmitt, "Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery," IEEE Trans. Commun., Vol. 27, pp. 1288-1295, Sept. 1979.
[13] F. M. Gardner, "Properties of Frequency Difference Detectors," IEEE Trans. Commun., Vol. 33, pp. 131-138, Feb. 1985.
[14] A. N. D'Andrea and U. Mengali, "Design of Quadricorrelators for Automatic Frequency Control Systems," IEEE Trans. Commun., Vol. 41, pp. 988-997, June 1993.
[15] T. Alberty and V. Hespel, "A New Pattern Jitter Free Frequency Error Detector," IEEE Trans. Commun., Vol. 37, pp. 159-163, Feb. 1989.
[16] H. Sari and S. Moridi, "New Phase and Frequency Detectors for Carrier Recovery in PSK and QAM Systems," IEEE Trans. Commun., Vol. 36, pp. 1035-1043, Sept. 1988.
[17] F. M. Gardner, "Frequency Detectors for Digital Demodulators via Maximum-likelihood Derivation," ESA Final Report: Part II, ESTEC Contract no. 8022/88/NL/DG, June 1990.
[18] C. R. Cahn, "Improving Frequency Acquisition of a Costas Loop," IEEE Trans. Commun., vol. COM-25, pp. 1453-1459, Dec 1977.
[19] A. V. Oppenheim and R. W. Schafer, Discrete-time Signal Processing, Prentice Hall, 1989.
[20] R. E. Best, Phase-Locked Loops: Theory, Design, and Applications, 2nd edition, New York, McGraw-Hill, 1993.
[21] B. C. Kuo, Automatic Control Systems, Fourth edition, Englewood Fliffs: Prentice-Hall, 1982.
[22] W. C. Lindsey and M. K. Simon, Telecommunications System Engineering, Englewood Fliffs: Prentice-Hall, 1973.
[23] E. A. Lee, D. G. Messerschmitt, Digital Communication, 2nd edition, Boston: Kluwer, 1994.
[24] A. Yamagishi, M. Ishikawa, T. Tsukahara, S. Date, "A 2-V, 2-GHz Low-Power Direct Digital Frequency Synthesizer Chip Set for Wireless Communication," IEEE Custom Integrated Circuits Conf., pp. 319-322, 1995.
[25] G. H. Kuo, "VLSI Implementation of Timing Recovery and Carrier Recovery for QAM/VSB Dual mode CATV System," Master Thesis, National Central University, 1998.
[26] C. C. Hung, "QAM/VSB Dual Mode Equalizer Design and Implementation," Master Thesis, National Central University, 1999.
[27] I. C. Yung, "Numerical Controlled Oscillator Using TSPC," Master Thesis, National Central University, 1995.
[28] H. T. Nicholas, III, and H. Samueli, "A 150-MHz direct Digital Frequency Synthesizer in 1.25-um CMOS with -90-dBc Spurious Performance," IEEE Journal of Solid-State Circuits, vol.26, no.12, pp.1959-1969, Dec. 1991.