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研究生:顏榮裕
研究生(外文):Rong-Yu Yen
論文名稱:應用於CATV系統中具有QAM/VSB模式的數位載波及時序回復電路設計
論文名稱(外文):Implementation of Carrier Recovery and Timing Recovery for QAM/VSB mode CATV System
指導教授:周世傑周世傑引用關係
指導教授(外文):Shyh-Jye Jou
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:中文
論文頁數:81
中文關鍵詞:載波回復時序回復鎖頻迴路相位解旋器驟斜率法鮑率時序回復二次相關頻率檢測器數值控制震盪器
外文關鍵詞:Carrier RecoveryTiming RecoveryFrequency Locked LoopDerotatorSteep Gradient MethodBaud-Rate TRQuadricorrelatorNumerically Controlled Oscillator
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在本篇論文中,我們提出一個可應用於有線電視上的載波回復電路以及時序回復電路架構,並且將此架構以硬體的方式實現。此架構不只適用於垂直正交振幅調變 (QAM, Quadrature Amplitude Modulation),同時也適用於殘旁邊帶振幅調變 (VSB, Vestigial Side-band Modulation)。在載波回復電路中,我們採用驟斜率方法 (Steep Gradient Method) 應用於相位檢測器 (Phase Detector) 上,而在時序回復電路中,我們則使用鮑率 (Baud-Rate) 相位檢測器。雖然此兩種方法在硬體時現實並不困難,然而為了要使電路更為簡單,我們另外也採用了方向理論 (Sign Algorithm),如此,原來電路中的乘法器將可以被二補數電路所取代。除此之外,為了增加載波回復電路的頻率追蹤範圍 (Acquisition Range),在殘旁邊帶振幅調變模式中,我們另外加入的一個鎖頻迴路 (Frequency Locked Loop);而在垂直正交振幅調變模式中,我們則加入了一對相位解旋/旋轉電路 (Dero-tator/Rotator Pair) 於載波回復電路之前。如此,依據C語言所架構的系統所得到的結果,此時載波回復電路可以具有100KHz的頻率追蹤範圍。最後,我們將載波回復電路、時序回復電路、鎖頻迴路、數值控制震盪器 (NCO, Numerically Controlled Oscillator) 以及混波器 (Mixer) 以硬體描述語言Verilog來描述,然後以Synopsys做電路的整合與最佳化。根據整合後的結果顯示,整個電路總共需要32,120閘。

In this thesis, an architecture design and hardware implementation for carrier re-covery (CR) and timing recovery (TR) in CATV system are proposed. It is not only suitable for Vestigal SideBand Modulation (VSB) but also suitable for Quadrature Amplitude Modulation (QAM). For CR, a Steep Gradient mothod is used, and for TR, a baud-rate TR is employed in our system. To reduce the hardware complexity, both of them use sign algorithm. Furthermore, to increase the acquisition range of CR, in VSB mode, a Frequency Locked Loop (FLL) is used while in QAM mode, a derota-tor/rotator pair is adopted. As a result, the CR can reach 100KHz acquisition range from simulation results. Finally, the whole design, which consists of a TR, a CR, a FLL, a loop controller, a mixer, and two NCOs, is desribed by Verilog hardware lan-guage and synthesized by Synopsys. From synthesis reports, the total gate counts are 32,120 gates.

1Introduction1
1.1Background1
1.2Motivation2
1.3Thesis Organization3
2Overview and Modification of the CATV Transceiver
Architecture5
2.1Transmitter5
2.2Receiver6
2.3Receiver Enhancement8
2.3.1The Modification in VSB Mode10
2.3.2The Modification in QAM Mode13
2.4Summary19
3Frequency Locked Loop20
3.1FLL20
3.1.1Loop Filter of FLL21
3.1.2Frequency Detector of FLL22
3.2Simulation Results by Matlab and C Code25
3.2.1Filter Design26
3.2.2Steady State Error30
3.3Hardware Implementation33
3.3.1Low Voltage Low Power33
3.3.2Frequency Detector33
3.3.3Simulation Results37
4Carrier Recovery Loop39
4.1Carrier Recovery39
4.1.1Introduction of PLL39
4.1.2Phase Detector Theorem42
4.2Derotator/Rotator46
4.2.1Passband Equalization46
4.2.2Structure of a Derotator/Rotator48
4.3Simulation Results by C Code50
4.3.1Bandwidth Adjustment51
4.3.2Latency of CR Loop52
4.4Hardware Implementation57
4.4.1Phase Detector57
4.4.2Prefilter and Bandwidth Controller58
4.4.3PI-filter59
4.4.4Synthesis Results59
5Timing Recovery62
5.1Phase Detector Theorem62
5.1.1Spectral-Line Method62
5.1.2MMSE Method64
5.1.3Baud-Rate Timing Recovery65
5.2Architecture of TR66
5.3Simulation Results68
6Overall Hardware Implementation72
6.1Overall Circuit Design72
6.1.1Loop Controller73
6.1.2NCO74
6.2Simulation Results75
7Conclusion78
Reference80

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