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研究生:葉峻源
研究生(外文):YEH, JIUNN-YUAN
論文名稱:WLAN及DECT射頻電路之研製
論文名稱(外文):RF Circuits for WLAN and DECT
指導教授:瞿大雄
指導教授(外文):Chu, TAH-HSIUNG
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電信工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:中文
論文頁數:106
中文關鍵詞:無線區域網路
外文關鍵詞:WLANDECT
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摘要
由於無線通信的大量需求,造成MMIC/RFIC的快速發展,多功能、體積小、成本低的高頻元件不斷的推出。在本論文中,首先使用GaAs MMIC製作無線區域網路(WLAN)卡射頻模組,其工作頻率為2.4GHz至2.483GHz之ISM頻帶。然而近年,為降低成本及系統化IC概念的形成,學術界及工業界紛紛投入CMOS射頻IC的研究,以期望基頻/中頻/射頻電路整合於一顆IC內。因此,本論文亦嘗試使用CMOS元件,設計適用及製作DECT射頻電路,驗證以CMOS製程製作DECT射頻IC的可行性。
本論文係由電路設計至電路製作及量測,對於WLAN及DECT射頻模組,做一全程的敘述及報告。由量測得知,研製之WLAN射頻模組在發射模式時可達18dBm之最大輸出功率,在接收模式時,當接收之QPSK信號強度為-80dBm時,其接收通信品質之EVM值為19.494%,符合規格要求。在CMOS射頻電路方面,單級之低雜訊放大器由量測得知,其增益約為10dB,雜訊指數約為3.3dB,串接兩單級低雜訊放大器,其增益約為20dB,雜訊指數約為3.4dB。CMOS混波器轉換增益約為11dB,單頻帶雜訊指數約為6~7dB,輸出三階互調交叉點約為7dBm。由射頻開關之量測顯示,由於基板之漏電流效應,造成CMOS電晶體較不適合用於射頻開關之設計。

Abstract
Due to the requirements of wireless communication market, the techniques of MMIC/RFIC grows rapidly in recent years. This leads the powerful, small and low cost MMIC/RFIC to become popular in the RF circuit design. In this thesis, transmitting and receiving RF circuits are implemented for WLAN RF module and DECT RF circuits. The WLAN RF module uses GaAs MMIC, which is operated in the ISM band ( 2.4GHz to 2.483GHz ). The DECT RF circuit uses the CMOS transistor to show its capability and difficulty in the frequency range of a few GHz. In the use of these types of two RF devices, this thesis describes the WLAN and DECT RF circuits with their circuit design, implementation and measurement.
Measurement results show that the WLAN RF module for transmitting has a maximum output power level of 18dBm, and for receiving has EVM value of 19.494% for a -80dBm QPSK signal. For the DECT CMOS RF circuits, measurement results show that the single stage CMOS LNA has about 10dB gain and 3.3 dB noise figure, and the e two stage LNA has about 20 dB gain and 3.4 dB noise figure. The CMOS mixer has about 11dB conversion gain, 6~7dB SSB noise figure, and 7dBm OIP3. The measurement results also show that the low substrate resistor in CMOS transistor may give the difficulty in the RF switch design.

目錄
第一章 簡介……………………………………………………………1
1.1 無線區域網路卡射頻電路概述……………………………….1
1.1.1 架構……………………………………………………….3
1.1.2 規格……………………………………………………….3
1.2 DECT射頻電路……………………………………………….4
1.2.1 架構………………………………………………………5
1.2.2 規格………………………………………………………5
1.3 CMOS元件特性………………………………………………7
第二章 無線區域網路卡射頻電路…………………………………19
2.1 電路設計……………………………………………………19
2.2 接收電路量測………………………………………………21
2.2.1 射頻量測……………………………………………..21
2.2.2 接收通信品質量測…………………………………..22
2.3 發射電路量測………………………………………………23
2.3.1 射頻量測…………………………………………….23
2.3.2 發射通信品質量測…………………………………24
2.4 整合測試…………………………………………………..24
2.4.1射頻模組整合測試………………………………………..25
2.4.2基頻/中頻/射頻模組整合測試…………………………25
第三章 DECT射頻電路……………………………………………..55
3.1 CMOS電晶體量測…………………………………………..55
3.1.1 佈局……………………………………………………..55
3.1.2 直流量測………………………………………………..56
3.1.3 散射參數及雜訊指數量測……………………………..56
3.1.4 混波量測………………………………………………..56
3.1.5 開關量測………………………………………………..56
3.2 低雜訊放大器………………………………………………..58
3.2.1 電路設計………………………………………………59
3.2.2 量測結果………………………………………………59
3.2 混波器……………………………………………………….59
3.3.1 電路設計………………………………………………60
3.3.2 量測結果……………………………………………….61
3.4 射頻開關……………………………………………………61
3.2.2 電路設計………………………………………………...62
3.2.3 量測結果………………………………………………...62
第四章 結論…………………………………………………………104
參考文獻……………………………………………………………105

參考文獻
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[2] 林盈錚,無線區域網路卡高頻/中頻模組之研製,碩士論文,台灣大學電機工程學研究所,民國八十五年六月。
[3] 羅立智,無線區域網路卡射頻模組之研製,碩士論文,台灣大學電機工程學研究所,民國八十七年六月。
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[15] Libra vol.2 User's Guide, EEsoft, Inc., Westlake Village , Calif., December 1992.
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