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研究生:姜國柱
研究生(外文):KUO-CHU CHIANG
論文名稱:生醫訊號放大器之積體電路設計
論文名稱(外文):Integrated Circuit Design of Biopotential Amplifier
指導教授:吳 建 平
指導教授(外文):CHIEN-PING WU
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:中文
論文頁數:65
中文關鍵詞:低頻雜訊偏移電壓截波穩定殘餘偏移
外文關鍵詞:low-frequency noiseoffset voltagechopper-stabilizedresidual offset
相關次數:
  • 被引用被引用:2
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在本論文中,針對生醫訊號,設計一以互補式金氧半積體電路製程製作之生醫訊號放大器。由於生醫訊號的頻寬多在低頻,且信號微小,故生醫訊號放大器的低頻雜訊必須很小。但由於互補式金氧半電晶體之半導體結構上的關係,其低頻雜訊比雙極性接面電晶體和接面場效電晶體高數十倍,互補式金氧半積體電路亦其有較大的偏移電壓,故應用於生醫訊號放大時應對這些特性給予特別的改善。
本研究所研製的生醫訊號放大器,是利用截波穩定技術,提供了生醫訊號放大器所需較低的低頻雜訊及偏移電壓,並且利用二階帶通濾波器,來濾除截波穩定開關所產生的殘餘偏移電壓。此外互補式金氧半電晶體也提供了高輸入阻抗。根據理論完成生醫訊號放大器各個部份的電路設計、模擬結果及佈局。最後證明在此架構下的生醫訊號放大器,完全符合生醫訊號量測之需要。
In the thesis, biopotential amplifier was designed for measurement of biopotential signals. Biopotential signals usually have very low low-frequency and very small amplitude. Hence, this biopotential amplifier must have very low low-frequency noise. Because CMOS transistors have much higher low-frequency noise than BJT and JFET, and the low-frequency noise must be reduced through circuit techniques. Besides, the offset voltage of the CMOS transistor has to be reduced.
The biopotential amplifier designed in this research used the chopper-stabilized technique to achieve low low-frequency noise and low DC offset voltage. A second-order bandpass filter was used to filter the residual offset induced by chopper-stabilized switches. Besides, CMOS transistors provide high input impedance. The biopotential amplifier has been designed, simulated, and the layout has been implemented successfully. Finally, it was proved that this biopotential amplifier completely matched the requirements for biopotential signals measurements.
摘要
第一章 緒論
1- 1 研究動機與目的………………………………1
1- 2 本論文的架構……………………………… 3
第二章 理論背景
2- 1 基本生醫訊號放大器之需求…………………5
2- 2 半導體元件的雜訊分析………………………7
2- 3 低雜訊技術……………………………………11
2- 4 低殘餘偏移(Residual Offset)技術………… 16
第三章 電路設計
3- 1 電路設計流程…………………………………21
3- 2 整體電路架構…………………………………22
3- 3 截波穩定(Chopper-Stabilized)電路技術……23
3- 4 前置放大器之設計……………………………26
3- 5 二階帶通濾波器之設計……..……………… 31
3- 6 偏壓電路之設計………………………………36
3- 7 非重疊時脈產生電路之設計..……………… 38
第四章 模擬結果與晶片佈局
4- 1 簡介……………………………………………40
4- 2 前置放大器的模擬結果………………………40
4- 3 二階帶通濾波器的模擬結果…………………45
4- 4 偏壓電路的模擬結果…………………………50
4- 5 非重疊時脈產生電路的模擬結果……………51
4- 6 整體電路的模擬結果…………………………52
4- 7 晶片佈局考量…………………………………54
4- 8 晶片佈局圖……………………………………56
第五章 結論
5- 1 總結……………………………………………61
5- 2 未來研究方向…………………………………62
參考文獻………………………………………… 63
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