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參考文獻 1. Andrew Grochowski, Debashis Bhattacharya, T. R. Viswanathan, and Ken Laker, “Integrated Circuit Testing for Quality Assurance in Manufacturing: History, Current Status, and Future Trends”, IEEE Transactions on Circuits and Systems, VOL.44, NO.8, pp.610~632, Aug 1997 2. “SR5000 Digital Stimulus/Response Tester User’s Manual”, Interface Technology Corp. 3. “STS 6000 System Description”, Credence Systems Corp., 1991. 4. Burnell West, and Tom Napier, “Sequencer Per Pin Test System Architecture”, IEEE International Test Conference, Paper 18.2, pp.355~361, 1990. 5. “Mixed Signal Tester Fundamental based on Teradyne A580 Model”, Teradyne Corp., 6. “SC212 System Description”, Credence Systems Corp. 7. “SR5500 User’s Manual”, Interface Technology Corp. 9. Makoto Suzuki, Norio Ohkubo, Toshinobu Shinbo, and Toshiaki Yamanaka, “A 1.5-ns 32-b CMOS ALU in Double Pass-Transistor Logic”, IEEE JSSC, VOL. 28, NO. 11, Nov. 1993 10. Hideaki Imada, Kenichi Fujisaki, Toshimi Ohsqwa, and Masaru Tsuto, “Generation Technique of 500MHz Ultral-high Speed Algorithmic Pattern”, IEEE International Test Conference, Paper25.2, pp. 677~684, 1996 11. William Low, and Andre Ivanov, “An Integrated Functional Tester for CMOS Logic”. IEEE CCECE, Paper 27.2, pp.453~456, 1993. 12. Hun-Hsien Chang and Jiin-Chuan Wu, “A 723-MHz 17.2mW CMOS Programmable Counter”, IEEE JSSC, VOL. 33, NO. 10, pp. 1572~1575, Oct. 1998 13. “Microcontroller Databook”, National Semiconductor, 1989 14. “Microprocessor Databook”, National Semiconductor, 1989
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